include/synopsys/dwcddr21mctl.h

21 	unsigned int	tpr0;		/* SDRAM Timing Parameters 0 */
48 #define DWCDDR21MCTL_CCR_ECCEN(x)	((x) << 0)
55 #define DWCDDR21MCTL_CCR_DFTLM(x)	(((x) & 0x3) << 15)
66 #define DWCDDR21MCTL_DCR_DDRMD(x)	((x) << 0)
67 #define DWCDDR21MCTL_DCR_DIO(x)		(((x) & 0x3) << 1)
68 #define DWCDDR21MCTL_DCR_DSIZE(x)	(((x) & 0x7) << 3)
69 #define DWCDDR21MCTL_DCR_SIO(x)		(((x) & 0x7) << 6)
71 #define DWCDDR21MCTL_DCR_RANKS(x)	(((x) & 0x3) << 10)
73 #define DWCDDR21MCTL_DCR_AMAP(x)	(((x) & 0x3) << 13)
74 #define DWCDDR21MCTL_DCR_RANK(x)	(((x) & 0x3) << 25)
75 #define DWCDDR21MCTL_DCR_CMD(x)		(((x) & 0xf) << 27)
81 #define DWCDDR21MCTL_IOCR_RTT(x)	(((x) & 0xf) << 0)
82 #define DWCDDR21MCTL_IOCR_DS(x)		(((x) & 0xf) << 4)
83 #define DWCDDR21MCTL_IOCR_TESTEN(x)	((x) << 0x8)
84 #define DWCDDR21MCTL_IOCR_RTTOH(x)	(((x) & 0x7) << 26)
92 #define DWCDDR21MCTL_CSR_DRIFT(x)	(((x) & 0x3ff) << 0)
102 #define DWCDDR21MCTL_DRR_TRFC(x)	(((x) & 0xff) << 0)
103 #define DWCDDR21MCTL_DRR_TRFPRD(x)	(((x) & 0xffff) << 8)
104 #define DWCDDR21MCTL_DRR_RFBURST(x)	(((x) & 0xf) << 24)
108  * SDRAM Timing Parameters Register 0
110 #define DWCDDR21MCTL_TPR0_TMRD(x)	(((x) & 0x3) << 0)
111 #define DWCDDR21MCTL_TPR0_TRTP(x)	(((x) & 0x7) << 2)
112 #define DWCDDR21MCTL_TPR0_TWTR(x)	(((x) & 0x7) << 5)
113 #define DWCDDR21MCTL_TPR0_TRP(x)	(((x) & 0xf) << 8)
114 #define DWCDDR21MCTL_TPR0_TRCD(x)	(((x) & 0xf) << 12)
115 #define DWCDDR21MCTL_TPR0_TRAS(x)	(((x) & 0x1f) << 16)
116 #define DWCDDR21MCTL_TPR0_TRRD(x)	(((x) & 0xf) << 21)
117 #define DWCDDR21MCTL_TPR0_TRC(x)	(((x) & 0x3f) << 25)
123 #define DWCDDR21MCTL_TPR1_TAOND(x)	(((x) & 0x3) << 0)
125 #define DWCDDR21MCTL_TPR1_TFAW(x)	(((x) & 0x3f) << 3)
126 #define DWCDDR21MCTL_TPR1_TRNKRTR(x)	(((x) & 0x3) << 12)
127 #define DWCDDR21MCTL_TPR1_TRNKWTW(x)	(((x) & 0x3) << 14)
128 #define DWCDDR21MCTL_TPR1_XCL(x)	(((x) & 0xf) << 23)
129 #define DWCDDR21MCTL_TPR1_XWR(x)	(((x) & 0xf) << 27)
135 #define DWCDDR21MCTL_TPR2_TXS(x)	(((x) & 0x3ff) << 0)
136 #define DWCDDR21MCTL_TPR2_TXP(x)	(((x) & 0x1f) << 10)
137 #define DWCDDR21MCTL_TPR2_TCKE(x)	(((x) & 0xf) << 15)
142 #define DWCDDR21MCTL_GDLLCR_DRES(x)	(((x) & 0x3) << 0)
143 #define DWCDDR21MCTL_GDLLCR_IPUMP(x)	(((x) & 0x7) << 2)
145 #define DWCDDR21MCTL_GDLLCR_DTC(x)	(((x) & 0x7) << 6)
146 #define DWCDDR21MCTL_GDLLCR_ATC(x)	(((x) & 0x3) << 9)
148 #define DWCDDR21MCTL_GDLLCR_MBIAS(x)	(((x) & 0xff) << 12)
149 #define DWCDDR21MCTL_GDLLCR_SBIAS(x)	(((x) & 0xff) << 20)
153  * DLL Control Register 0-9
155 #define DWCDDR21MCTL_DLLCR_SFBDLY(x)	(((x) & 0x7) << 0)
156 #define DWCDDR21MCTL_DLLCR_SFWDLY(x)	(((x) & 0x7) << 3)
157 #define DWCDDR21MCTL_DLLCR_MFBDLY(x)	(((x) & 0x7) << 6)
158 #define DWCDDR21MCTL_DLLCR_MFWDLY(x)	(((x) & 0x7) << 9)
159 #define DWCDDR21MCTL_DLLCR_SSTART(x)	(((x) & 0x3) << 12)
160 #define DWCDDR21MCTL_DLLCR_PHASE(x)	(((x) & 0xf) << 14)
168 #define DWCDDR21MCTL_RSLR_SL0(x)	(((x) & 0x7) << 0)
169 #define DWCDDR21MCTL_RSLR_SL1(x)	(((x) & 0x7) << 3)
170 #define DWCDDR21MCTL_RSLR_SL2(x)	(((x) & 0x7) << 6)
171 #define DWCDDR21MCTL_RSLR_SL3(x)	(((x) & 0x7) << 9)
172 #define DWCDDR21MCTL_RSLR_SL4(x)	(((x) & 0x7) << 12)
173 #define DWCDDR21MCTL_RSLR_SL5(x)	(((x) & 0x7) << 15)
174 #define DWCDDR21MCTL_RSLR_SL6(x)	(((x) & 0x7) << 18)
175 #define DWCDDR21MCTL_RSLR_SL7(x)	(((x) & 0x7) << 21)
176 #define DWCDDR21MCTL_RSLR_SL8(x)	(((x) & 0x7) << 24)
181 #define DWCDDR21MCTL_RDGR_DQSSEL0(x)	(((x) & 0x3) << 0)
182 #define DWCDDR21MCTL_RDGR_DQSSEL1(x)	(((x) & 0x3) << 2)
183 #define DWCDDR21MCTL_RDGR_DQSSEL2(x)	(((x) & 0x3) << 4)
184 #define DWCDDR21MCTL_RDGR_DQSSEL3(x)	(((x) & 0x3) << 6)
185 #define DWCDDR21MCTL_RDGR_DQSSEL4(x)	(((x) & 0x3) << 8)
186 #define DWCDDR21MCTL_RDGR_DQSSEL5(x)	(((x) & 0x3) << 10)
187 #define DWCDDR21MCTL_RDGR_DQSSEL6(x)	(((x) & 0x3) << 12)
188 #define DWCDDR21MCTL_RDGR_DQSSEL7(x)	(((x) & 0x3) << 14)
189 #define DWCDDR21MCTL_RDGR_DQSSEL8(x)	(((x) & 0x3) << 16)
194 #define DWCDDR21MCTL_DQTR_DQDLY0(x)	(((x) & 0xf) << 0)
195 #define DWCDDR21MCTL_DQTR_DQDLY1(x)	(((x) & 0xf) << 4)
196 #define DWCDDR21MCTL_DQTR_DQDLY2(x)	(((x) & 0xf) << 8)
197 #define DWCDDR21MCTL_DQTR_DQDLY3(x)	(((x) & 0xf) << 12)
198 #define DWCDDR21MCTL_DQTR_DQDLY4(x)	(((x) & 0xf) << 16)
199 #define DWCDDR21MCTL_DQTR_DQDLY5(x)	(((x) & 0xf) << 20)
200 #define DWCDDR21MCTL_DQTR_DQDLY6(x)	(((x) & 0xf) << 24)
201 #define DWCDDR21MCTL_DQTR_DQDLY7(x)	(((x) & 0xf) << 28)
206 #define DWCDDR21MCTL_DQSTR_DQSDLY0(x)	(((x) & 0x7) << 0)
207 #define DWCDDR21MCTL_DQSTR_DQSDLY1(x)	(((x) & 0x7) << 3)
208 #define DWCDDR21MCTL_DQSTR_DQSDLY2(x)	(((x) & 0x7) << 6)
209 #define DWCDDR21MCTL_DQSTR_DQSDLY3(x)	(((x) & 0x7) << 9)
210 #define DWCDDR21MCTL_DQSTR_DQSDLY4(x)	(((x) & 0x7) << 12)
211 #define DWCDDR21MCTL_DQSTR_DQSDLY5(x)	(((x) & 0x7) << 15)
212 #define DWCDDR21MCTL_DQSTR_DQSDLY6(x)	(((x) & 0x7) << 18)
213 #define DWCDDR21MCTL_DQSTR_DQSDLY7(x)	(((x) & 0x7) << 21)
214 #define DWCDDR21MCTL_DQSTR_DQSDLY8(x)	(((x) & 0x7) << 24)
219 #define DWCDDR21MCTL_DQSBTR_DQSDLY0(x)	(((x) & 0x7) << 0)
220 #define DWCDDR21MCTL_DQSBTR_DQSDLY1(x)	(((x) & 0x7) << 3)
221 #define DWCDDR21MCTL_DQSBTR_DQSDLY2(x)	(((x) & 0x7) << 6)
222 #define DWCDDR21MCTL_DQSBTR_DQSDLY3(x)	(((x) & 0x7) << 9)
223 #define DWCDDR21MCTL_DQSBTR_DQSDLY4(x)	(((x) & 0x7) << 12)
224 #define DWCDDR21MCTL_DQSBTR_DQSDLY5(x)	(((x) & 0x7) << 15)
225 #define DWCDDR21MCTL_DQSBTR_DQSDLY6(x)	(((x) & 0x7) << 18)
226 #define DWCDDR21MCTL_DQSBTR_DQSDLY7(x)	(((x) & 0x7) << 21)
227 #define DWCDDR21MCTL_DQSBTR_DQSDLY8(x)	(((x) & 0x7) << 24)
232 #define DWCDDR21MCTL_ODTCR_RDODT0(x)	(((x) & 0xf) << 0)
233 #define DWCDDR21MCTL_ODTCR_RDODT1(x)	(((x) & 0xf) << 4)
234 #define DWCDDR21MCTL_ODTCR_RDODT2(x)	(((x) & 0xf) << 8)
235 #define DWCDDR21MCTL_ODTCR_RDODT3(x)	(((x) & 0xf) << 12)
236 #define DWCDDR21MCTL_ODTCR_WDODT0(x)	(((x) & 0xf) << 16)
237 #define DWCDDR21MCTL_ODTCR_WDODT1(x)	(((x) & 0xf) << 20)
238 #define DWCDDR21MCTL_ODTCR_WDODT2(x)	(((x) & 0xf) << 24)
239 #define DWCDDR21MCTL_ODTCR_WDODT3(x)	(((x) & 0xf) << 28)
244 #define DWCDDR21MCTL_DTR0_DTBYTE0(x)	(((x) & 0xff) << 0)	/* def: 0x11 */
245 #define DWCDDR21MCTL_DTR0_DTBYTE1(x)	(((x) & 0xff) << 8)	/* def: 0xee */
246 #define DWCDDR21MCTL_DTR0_DTBYTE2(x)	(((x) & 0xff) << 16)	/* def: 0x22 */
247 #define DWCDDR21MCTL_DTR0_DTBYTE3(x)	(((x) & 0xff) << 24)	/* def: 0xdd */
249 #define DWCDDR21MCTL_DTR1_DTBYTE4(x)	(((x) & 0xff) << 0)	/* def: 0x44 */
250 #define DWCDDR21MCTL_DTR1_DTBYTE5(x)	(((x) & 0xff) << 8)	/* def: 0xbb */
251 #define DWCDDR21MCTL_DTR1_DTBYTE6(x)	(((x) & 0xff) << 16)	/* def: 0x88 */
252 #define DWCDDR21MCTL_DTR1_DTBYTE7(x)	(((x) & 0xff) << 24)	/* def: 0x77 */
257 #define DWCDDR21MCTL_DTAR_DTCOL(x)	(((x) & 0xfff) << 0)
258 #define DWCDDR21MCTL_DTAR_DTROW(x)	(((x) & 0xffff) << 12)
259 #define DWCDDR21MCTL_DTAR_DTBANK(x)	(((x) & 0x7) << 28)
264 #define DWCDDR21MCTL_MR_BL(x)		(((x) & 0x7) << 0)
266 #define DWCDDR21MCTL_MR_CL(x)		(((x) & 0x7) << 4)
269 #define DWCDDR21MCTL_MR_WR(x)		(((x) & 0x7) << 9)
275 #define DWCDDR21MCTL_EMR_DE(x)		((x) << 0)
278 #define DWCDDR21MCTL_EMR_AL(x)		(((x) & 0x7) << 3)
280 #define DWCDDR21MCTL_EMR_OCD(x)		(((x) & 0x7) << 7)
288 #define DWCDDR21MCTL_EMR_RTT_DISABLED	(EMR_RTT6(0) | EMR_RTT2(0))
289 #define DWCDDR21MCTL_EMR_RTT_75		(EMR_RTT6(0) | EMR_RTT2(1))
290 #define DWCDDR21MCTL_EMR_RTT_150	(EMR_RTT6(1) | EMR_RTT2(0))
296 #define DWCDDR21MCTL_EMR2_PASR(x)	(((x) & 0x7) << 0)
301  * Extended Mode register 3: [15:0] reserved for JEDEC.
305  * Host port Configuration register 0-31
307 #define DWCDDR21MCTL_HPCR_HPBL(x)	(((x) & 0xf) << 0)
310  * Priority Queue Configuration register 0-7
312 #define DWCDDR21MCTL_HPCR_TOUT(x)	(((x) & 0xf) << 0)
313 #define DWCDDR21MCTL_HPCR_TOUTX(x)	(((x) & 0x3) << 8)
314 #define DWCDDR21MCTL_HPCR_LPQS(x)	(((x) & 0x3) << 10)
315 #define DWCDDR21MCTL_HPCR_PQBL(x)	(((x) & 0xff) << 12)
316 #define DWCDDR21MCTL_HPCR_SWAIT(x)	(((x) & 0x1f) << 20)
317 #define DWCDDR21MCTL_HPCR_INTRPT(x)	(((x) & 0x7) << 25)
323 #define DWCDDR21MCTL_MMGCR_UHPP(x)	(((x) & 0x3) << 0)