Lines Matching full:30
356 #define SICRH_ESDHC_A_SD (0 << 30)
357 #define SICRH_ESDHC_A_GTM (1 << 30)
358 #define SICRH_ESDHC_A_GPIO (3 << 30)
390 #define SICR_1_UART1_UART1S (0 << (30-2))
391 #define SICR_1_UART1_UART1RTS (1 << (30-2))
392 #define SICR_1_I2C_I2C (0 << (30-4))
393 #define SICR_1_I2C_CKSTOP (1 << (30-4))
394 #define SICR_1_IRQ_A_IRQ (0 << (30-6))
395 #define SICR_1_IRQ_A_MCP (1 << (30-6))
396 #define SICR_1_IRQ_B_IRQ (0 << (30-8))
397 #define SICR_1_IRQ_B_CKSTOP (1 << (30-8))
398 #define SICR_1_GPIO_A_GPIO (0 << (30-10))
399 #define SICR_1_GPIO_A_SD (2 << (30-10))
400 #define SICR_1_GPIO_A_DDR (3 << (30-10))
401 #define SICR_1_GPIO_B_GPIO (0 << (30-12))
402 #define SICR_1_GPIO_B_SD (2 << (30-12))
403 #define SICR_1_GPIO_B_QE (3 << (30-12))
404 #define SICR_1_GPIO_C_GPIO (0 << (30-14))
405 #define SICR_1_GPIO_C_CAN (1 << (30-14))
406 #define SICR_1_GPIO_C_DDR (2 << (30-14))
407 #define SICR_1_GPIO_C_LCS (3 << (30-14))
408 #define SICR_1_GPIO_D_GPIO (0 << (30-16))
409 #define SICR_1_GPIO_D_CAN (1 << (30-16))
410 #define SICR_1_GPIO_D_DDR (2 << (30-16))
411 #define SICR_1_GPIO_D_LCS (3 << (30-16))
412 #define SICR_1_GPIO_E_GPIO (0 << (30-18))
413 #define SICR_1_GPIO_E_CAN (1 << (30-18))
414 #define SICR_1_GPIO_E_DDR (2 << (30-18))
415 #define SICR_1_GPIO_E_LCS (3 << (30-18))
416 #define SICR_1_GPIO_F_GPIO (0 << (30-20))
417 #define SICR_1_GPIO_F_CAN (1 << (30-20))
418 #define SICR_1_GPIO_F_CK (2 << (30-20))
419 #define SICR_1_USB_A_USBDR (0 << (30-22))
420 #define SICR_1_USB_A_UART2S (1 << (30-22))
421 #define SICR_1_USB_B_USBDR (0 << (30-24))
422 #define SICR_1_USB_B_UART2S (1 << (30-24))
423 #define SICR_1_USB_B_UART2RTS (2 << (30-24))
424 #define SICR_1_USB_C_USBDR (0 << (30-26))
425 #define SICR_1_USB_C_QE_EXT (3 << (30-26))
426 #define SICR_1_FEC1_FEC1 (0 << (30-28))
427 #define SICR_1_FEC1_GTM (1 << (30-28))
428 #define SICR_1_FEC1_GPIO (2 << (30-28))
429 #define SICR_1_FEC2_FEC2 (0 << (30-30))
430 #define SICR_1_FEC2_GTM (1 << (30-30))
431 #define SICR_1_FEC2_GPIO (2 << (30-30))
433 #define SICR_2_FEC3_FEC3 (0 << (30-0))
434 #define SICR_2_FEC3_TMR (1 << (30-0))
435 #define SICR_2_FEC3_GPIO (2 << (30-0))
436 #define SICR_2_HDLC1_A_HDLC1 (0 << (30-2))
437 #define SICR_2_HDLC1_A_GPIO (1 << (30-2))
438 #define SICR_2_HDLC1_A_TDM1 (2 << (30-2))
439 #define SICR_2_ELBC_A_LA (0 << (30-4))
440 #define SICR_2_ELBC_B_LCLK (0 << (30-6))
441 #define SICR_2_HDLC2_A_HDLC2 (0 << (30-8))
442 #define SICR_2_HDLC2_A_GPIO (0 << (30-8))
443 #define SICR_2_HDLC2_A_TDM2 (0 << (30-8))
445 #define SICR_2_USB_D_USBDR (0 << (30-12))
446 #define SICR_2_USB_D_GPIO (2 << (30-12))
447 #define SICR_2_USB_D_QE_BRG (3 << (30-12))
448 #define SICR_2_PCI_PCI (0 << (30-14))
449 #define SICR_2_PCI_CPCI_HS (2 << (30-14))
450 #define SICR_2_HDLC1_B_HDLC1 (0 << (30-16))
451 #define SICR_2_HDLC1_B_GPIO (1 << (30-16))
452 #define SICR_2_HDLC1_B_QE_BRG (2 << (30-16))
453 #define SICR_2_HDLC1_B_TDM1 (3 << (30-16))
454 #define SICR_2_HDLC1_C_HDLC1 (0 << (30-18))
455 #define SICR_2_HDLC1_C_GPIO (1 << (30-18))
456 #define SICR_2_HDLC1_C_TDM1 (2 << (30-18))
457 #define SICR_2_HDLC2_B_HDLC2 (0 << (30-20))
458 #define SICR_2_HDLC2_B_GPIO (1 << (30-20))
459 #define SICR_2_HDLC2_B_QE_BRG (2 << (30-20))
460 #define SICR_2_HDLC2_B_TDM2 (3 << (30-20))
461 #define SICR_2_HDLC2_C_HDLC2 (0 << (30-22))
462 #define SICR_2_HDLC2_C_GPIO (1 << (30-22))
463 #define SICR_2_HDLC2_C_TDM2 (2 << (30-22))
464 #define SICR_2_HDLC2_C_QE_BRG (3 << (30-22))
465 #define SICR_2_QUIESCE_B (0 << (30-24))
560 #define HRCWL_DDRCM_SHIFT 30
891 #define SPMR_DDRCM_SHIFT 30
944 #define SCCR_TSEC1CM_SHIFT 30
972 #define SCCR_TSEC1CM_SHIFT 30
993 #define SCCR_TSEC1CM_SHIFT 30
1039 #define SCCR_TSEC1CM_SHIFT 30
1158 #define TIMING_CFG0_RWT_SHIFT 30