Lines Matching +full:- +full:30
2 * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
28 * IMMRBAR - Internal Memory Register Base Address
40 * LAWBAR - Local Access Window Base Address Register
54 * SPRIDR - System Part and Revision ID Register
95 * SPCR - System Priority Configuration Register
99 #define SPCR_PCIHPE_SHIFT (31-3)
102 #define SPCR_PCIPR_SHIFT (31-7)
104 #define SPCR_OPT_SHIFT (31-8)
107 #define SPCR_TBEN_SHIFT (31-9)
110 #define SPCR_COREPR_SHIFT (31-11)
113 /* SPCR bits - MPC8349 specific */
116 #define SPCR_TSEC1DP_SHIFT (31-19)
119 #define SPCR_TSEC1BDP_SHIFT (31-21)
122 #define SPCR_TSEC1EP_SHIFT (31-23)
125 #define SPCR_TSEC2DP_SHIFT (31-27)
128 #define SPCR_TSEC2BDP_SHIFT (31-29)
131 #define SPCR_TSEC2EP_SHIFT (31-31)
135 /* SPCR bits - MPC8308, MPC831x and MPC837x specific */
138 #define SPCR_TSECDP_SHIFT (31-19)
141 #define SPCR_TSECBDP_SHIFT (31-21)
144 #define SPCR_TSECEP_SHIFT (31-23)
147 /* SICRL/H - System I/O Configuration Register Low/High
150 /* SICRL bits - MPC8349 specific */
168 /* SICRH bits - MPC8349 specific */
196 /* SICRL bits - MPC8360 specific */
203 /* SICRH bits - MPC8360 specific */
213 /* SICRL bits - MPC832x specific */
221 /* SICRL bits - MPC8313 specific */
235 /* SICRH bits - MPC8313 specific */
253 /* SICRL bits - MPC8315 specific */
270 /* SICRH bits - MPC8315 specific */
288 /* SICRL bits - MPC837x specific */
318 /* SICRH bits - MPC837x specific */
341 /* SICRL bits - MPC8308 specific */
355 /* SICRH bits - MPC8308 specific */
356 #define SICRH_ESDHC_A_SD (0 << 30)
357 #define SICRH_ESDHC_A_GTM (1 << 30)
358 #define SICRH_ESDHC_A_GPIO (3 << 30)
390 #define SICR_1_UART1_UART1S (0 << (30-2))
391 #define SICR_1_UART1_UART1RTS (1 << (30-2))
392 #define SICR_1_I2C_I2C (0 << (30-4))
393 #define SICR_1_I2C_CKSTOP (1 << (30-4))
394 #define SICR_1_IRQ_A_IRQ (0 << (30-6))
395 #define SICR_1_IRQ_A_MCP (1 << (30-6))
396 #define SICR_1_IRQ_B_IRQ (0 << (30-8))
397 #define SICR_1_IRQ_B_CKSTOP (1 << (30-8))
398 #define SICR_1_GPIO_A_GPIO (0 << (30-10))
399 #define SICR_1_GPIO_A_SD (2 << (30-10))
400 #define SICR_1_GPIO_A_DDR (3 << (30-10))
401 #define SICR_1_GPIO_B_GPIO (0 << (30-12))
402 #define SICR_1_GPIO_B_SD (2 << (30-12))
403 #define SICR_1_GPIO_B_QE (3 << (30-12))
404 #define SICR_1_GPIO_C_GPIO (0 << (30-14))
405 #define SICR_1_GPIO_C_CAN (1 << (30-14))
406 #define SICR_1_GPIO_C_DDR (2 << (30-14))
407 #define SICR_1_GPIO_C_LCS (3 << (30-14))
408 #define SICR_1_GPIO_D_GPIO (0 << (30-16))
409 #define SICR_1_GPIO_D_CAN (1 << (30-16))
410 #define SICR_1_GPIO_D_DDR (2 << (30-16))
411 #define SICR_1_GPIO_D_LCS (3 << (30-16))
412 #define SICR_1_GPIO_E_GPIO (0 << (30-18))
413 #define SICR_1_GPIO_E_CAN (1 << (30-18))
414 #define SICR_1_GPIO_E_DDR (2 << (30-18))
415 #define SICR_1_GPIO_E_LCS (3 << (30-18))
416 #define SICR_1_GPIO_F_GPIO (0 << (30-20))
417 #define SICR_1_GPIO_F_CAN (1 << (30-20))
418 #define SICR_1_GPIO_F_CK (2 << (30-20))
419 #define SICR_1_USB_A_USBDR (0 << (30-22))
420 #define SICR_1_USB_A_UART2S (1 << (30-22))
421 #define SICR_1_USB_B_USBDR (0 << (30-24))
422 #define SICR_1_USB_B_UART2S (1 << (30-24))
423 #define SICR_1_USB_B_UART2RTS (2 << (30-24))
424 #define SICR_1_USB_C_USBDR (0 << (30-26))
425 #define SICR_1_USB_C_QE_EXT (3 << (30-26))
426 #define SICR_1_FEC1_FEC1 (0 << (30-28))
427 #define SICR_1_FEC1_GTM (1 << (30-28))
428 #define SICR_1_FEC1_GPIO (2 << (30-28))
429 #define SICR_1_FEC2_FEC2 (0 << (30-30))
430 #define SICR_1_FEC2_GTM (1 << (30-30))
431 #define SICR_1_FEC2_GPIO (2 << (30-30))
433 #define SICR_2_FEC3_FEC3 (0 << (30-0))
434 #define SICR_2_FEC3_TMR (1 << (30-0))
435 #define SICR_2_FEC3_GPIO (2 << (30-0))
436 #define SICR_2_HDLC1_A_HDLC1 (0 << (30-2))
437 #define SICR_2_HDLC1_A_GPIO (1 << (30-2))
438 #define SICR_2_HDLC1_A_TDM1 (2 << (30-2))
439 #define SICR_2_ELBC_A_LA (0 << (30-4))
440 #define SICR_2_ELBC_B_LCLK (0 << (30-6))
441 #define SICR_2_HDLC2_A_HDLC2 (0 << (30-8))
442 #define SICR_2_HDLC2_A_GPIO (0 << (30-8))
443 #define SICR_2_HDLC2_A_TDM2 (0 << (30-8))
444 /* bits 10-11 unused */
445 #define SICR_2_USB_D_USBDR (0 << (30-12))
446 #define SICR_2_USB_D_GPIO (2 << (30-12))
447 #define SICR_2_USB_D_QE_BRG (3 << (30-12))
448 #define SICR_2_PCI_PCI (0 << (30-14))
449 #define SICR_2_PCI_CPCI_HS (2 << (30-14))
450 #define SICR_2_HDLC1_B_HDLC1 (0 << (30-16))
451 #define SICR_2_HDLC1_B_GPIO (1 << (30-16))
452 #define SICR_2_HDLC1_B_QE_BRG (2 << (30-16))
453 #define SICR_2_HDLC1_B_TDM1 (3 << (30-16))
454 #define SICR_2_HDLC1_C_HDLC1 (0 << (30-18))
455 #define SICR_2_HDLC1_C_GPIO (1 << (30-18))
456 #define SICR_2_HDLC1_C_TDM1 (2 << (30-18))
457 #define SICR_2_HDLC2_B_HDLC2 (0 << (30-20))
458 #define SICR_2_HDLC2_B_GPIO (1 << (30-20))
459 #define SICR_2_HDLC2_B_QE_BRG (2 << (30-20))
460 #define SICR_2_HDLC2_B_TDM2 (3 << (30-20))
461 #define SICR_2_HDLC2_C_HDLC2 (0 << (30-22))
462 #define SICR_2_HDLC2_C_GPIO (1 << (30-22))
463 #define SICR_2_HDLC2_C_TDM2 (2 << (30-22))
464 #define SICR_2_HDLC2_C_QE_BRG (3 << (30-22))
465 #define SICR_2_QUIESCE_B (0 << (30-24))
470 * SWCRR - System Watchdog Control Register
486 * SWCNR - System Watchdog Counter Register
495 * SWSRR - System Watchdog Service Register
501 * ACR - Arbiter Configuration Register
504 #define ACR_COREDIS_SHIFT (31-7)
506 #define ACR_PIPE_DEP_SHIFT (31-15)
508 #define ACR_PCI_RPTCNT_SHIFT (31-19)
510 #define ACR_RPTCNT_SHIFT (31-23)
512 #define ACR_APARK_SHIFT (31-27)
514 #define ACR_PARKM_SHIFT (31-31)
517 * ATR - Arbiter Timers Register
525 * AER - Arbiter Event Register
538 * AEATR - Arbiter Event Address Register
552 * HRCWL - Hard Reset Configuration Word Low
560 #define HRCWL_DDRCM_SHIFT 30
718 * HRCWH - Hardware Reset Configuration Word High
820 * RSR - Reset Status Register
862 * RMR - Reset Mode Register
870 * RCR - Reset Control Register
879 * RCER - Reset Control Enable Register
886 * SPMR - System PLL Mode Register
891 #define SPMR_DDRCM_SHIFT 30
906 * OCCR - Output Clock Control Register
929 * SCCR - System Clock Control Register
942 /* SCCR bits - MPC834x specific */
944 #define SCCR_TSEC1CM_SHIFT 30
972 #define SCCR_TSEC1CM_SHIFT 30
991 /* SCCR bits - MPC8315/MPC8308 specific */
993 #define SCCR_TSEC1CM_SHIFT 30
1037 /* SCCR bits - MPC837x specific */
1039 #define SCCR_TSEC1CM_SHIFT 30
1076 /* SCCR bits - MPC8309 specific */
1107 * CSn_BDNS - Chip Select memory Bounds Register
1115 * CSn_CONFIG - Chip Select Configuration Register
1155 * TIMING_CFG_0 - DDR SDRAM Timing Configuration 0
1158 #define TIMING_CFG0_RWT_SHIFT 30
1175 * TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
1202 * TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
1224 * TIMING_CFG_3 - DDR SDRAM Timing Configuration 3
1230 * DDR_SDRAM_CFG - DDR SDRAM Control Configuration
1257 * DDR_SDRAM_MODE - DDR SDRAM Mode Register
1296 * DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register
1303 * DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register
1312 * ECC_ERR_INJECT - Memory data path error injection mask ECC
1323 * CAPTURE_ECC - Memory data path read capture ECC
1329 * ERR_DETECT - Memory error detect
1333 /* Multiple-Bit Error */
1335 /* Single-Bit ECC Error Pickup */
1341 * ERR_DISABLE - Memory error disable
1343 /* Multiple-Bit ECC Error Disable */
1345 /* Sinle-Bit ECC Error disable */
1354 * ERR_INT_EN - Memory error interrupt enable
1356 /* Multiple-Bit ECC Error Interrupt Enable */
1358 /* Single-Bit ECC Error Interrupt Enable */
1367 * CAPTURE_ATTRIBUTES - Memory error attributes capture
1402 * ERR_SBE - Single bit ECC memory error management
1404 /* Single-Bit Error Threshold 0..255 */
1412 * CONFIG_ADDRESS - PCI Config Address Register
1425 * POTAR - PCI Outbound Translation Address Register
1430 * POBAR - PCI Outbound Base Address Register
1435 * POCMR - PCI Outbound Comparision Mask Register
1438 /* 0-memory space 1-I/O space */
1441 #define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */
1466 * PITAR - PCI Inbound Translation Address Register
1471 * PIBAR - PCI Inbound Base/Extended Address Register
1477 * PIWAR - PCI Inbound Windows Attributes Register
1510 * PMCCR1 - PCI Configuration Register 1
1515 * DDRCDR - DDR Control Driver Register