Lines Matching +full:0 +full:x4a030000

15 #define OMAP_XHCI_BASE 0x488d0000
16 #define OMAP_OCP1_SCP_BASE 0x4A081000
17 #define OMAP_OTG_WRAPPER_BASE 0x488c0000
18 #elif CONFIG_USB_XHCI_DRA7XX_INDEX == 0
19 #define OMAP_XHCI_BASE 0x48890000
20 #define OMAP_OCP1_SCP_BASE 0x4A084c00
21 #define OMAP_OTG_WRAPPER_BASE 0x48880000
24 #define OMAP_XHCI_BASE 0x483d0000
25 #define OMAP_OCP1_SCP_BASE 0x483E8000
26 #define OMAP_OTG_WRAPPER_BASE 0x483dc100
29 #define OMAP_XHCI_BASE 0x4a030000
30 #define OMAP_OCP1_SCP_BASE 0x4a084c00
31 #define OMAP_OTG_WRAPPER_BASE 0x4A020000
35 #define	PLL_REGM_MASK		0x001FFE00
36 #define	PLL_REGM_SHIFT		0x9
37 #define	PLL_REGM_F_MASK		0x0003FFFF
38 #define	PLL_REGM_F_SHIFT	0x0
39 #define	PLL_REGN_MASK		0x000001FE
40 #define	PLL_REGN_SHIFT		0x1
41 #define	PLL_SELFREQDCO_MASK	0x0000000E
42 #define	PLL_SELFREQDCO_SHIFT	0x1
43 #define	PLL_SD_MASK		0x0003FC00
44 #define	PLL_SD_SHIFT		0x9
45 #define	SET_PLL_GO		0x1
46 #define	PLL_TICOPWDN		0x10000
47 #define	PLL_LOCK		0x2
48 #define	PLL_IDLE		0x1
50 #define USB3_PWRCTL_CLK_CMD_MASK	0x3FE000
51 #define USB3_PWRCTL_CLK_FREQ_MASK	0xFFC
64 #define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4)
67 #define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2)
70 #define USBOTGSS_COREIRQ_EN	(1 << 0)
73 #define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN	(1 << 0)
92 	u32 sysconfig; /* offset of 0x10 */
97 	u32 irqstatus_raw_0; /* offset of 0x24 */
102 	u32 irqstatus_raw_1; /* offset of 0x34 */
109 	u32 utmi_otg_ctrl; /* offset of 0x80 */
114 	u32 mram_offset; /* offset of 0x100 */