include/linux/serial_reg.h

6  * SPDX-License-Identifier:	GPL-2.0+
42 #define UART_IIR_RX_TIMEOUT	0x0c /* OMAP RX Timeout interrupt */
53  *	RX:76 = 00  01  10  11	TX:54 = 00  01  10  11
117 #define UART_MCR_AFE		0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
127 #define UART_LSR_THRE		0x20 /* Transmit-hold-register empty */
184 #define UART_TRG	0	/* FCTR bit 7 selects Rx or Tx
206 #define UART_FCTR_TX_INT	0x08  /* Tx interrupt type select */
207 #define UART_FCTR_TRGA		0x00  /* Tx/Rx 550 trigger table select */
208 #define UART_FCTR_TRGB		0x10  /* Tx/Rx 650 trigger table select */
209 #define UART_FCTR_TRGC		0x20  /* Tx/Rx 654 trigger table select */
210 #define UART_FCTR_TRGD		0x30  /* Tx/Rx 850 programmable trigger select */
211 #define UART_FCTR_SCR_SWAP	0x40  /* Scratch pad register swap */
219 #define UART_EMSR_FIFO_COUNT	0x01  /* Rx/Tx select */
223  * The Intel XScale on-chip UARTs define these bits
238  * Intel MID on-chip HSU (High Speed UART) defined bits
278 #define UART_NMR	0x0D	/* Nine-bit Mode Register */
294  * These definitions are for the RSA-DV II/S card, from
296  * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
299 #define UART_RSA_BASE (-8)
303 #define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */
310 #define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */
311 #define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */
312 #define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */
318 #define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */
319 #define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */
320 #define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */
321 #define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */
322 #define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */
323 #define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */
355 #define UART_OMAP_WER		0x17	/* Wake-up enable register */
362 #define UART_OMAP_MDR1_16X_ABAUD_MODE	0x02	/* UART 16x auto-baud */
384 #define UART_EXAR_TXTRG		0x0a	/* Tx FIFO trigger level write-only */
385 #define UART_EXAR_RXTRG		0x0b	/* Rx FIFO trigger level write-only */