u-boot/include/fsl_tgec.h

2  * Copyright 2009-2011 Freescale Semiconductor, Inc.
5  * SPDX-License-Identifier:	GPL-2.0+
18 	u32	mac_addr_0;	/* Lower 32 bits of 48-bit MAC address */
19 	u32	mac_addr_1;	/* Upper 16 bits of 48-bit MAC address */
26 	u32	tx_ipg_length;	/* Transmitter inter-packet-gap register */
27 	u32	mac_addr_2;	/* Lower 32 bits of the 2nd 48-bit MAC addr */
28 	u32	mac_addr_3;	/* Upper 16 bits of the 2nd 48-bit MAC addr */
34 	u32	tx_frame_u;	/* Tx frame counter upper */
35 	u32	tx_frame_l;	/* Tx frame counter lower */
42 	u32	tx_pause_frame_u; /* Tx valid pause frame upper */
43 	u32	tx_pause_frame_l; /* Tx valid pause frame lower */
50 	u32	tx_vlan_u;	/* Tx VLAN frame upper */
51 	u32	tx_vlan_l;	/* Tx VLAN frame lower */
54 	u32	tx_oct_u;	/* Tx octets upper */
55 	u32	tx_oct_l;	/* Tx octets lower */
64 	u32	tx_frame_err_u;	/* Tx frame error upper */
65 	u32	tx_frame_err_l;	/* Tx frame error lower */
66 	u32	tx_uni_u;	/* Tx unicast frame upper */
67 	u32	tx_uni_l;	/* Tx unicast frame lower */
68 	u32	tx_multi_u;	/* Tx multicast frame upper */
69 	u32	tx_multi_l;	/* Tx multicast frame lower */
70 	u32	tx_brd_u;	/* Tx broadcast frame upper */
71 	u32	tx_brd_l;	/* Tx broadcast frame lower */
105 /* EC10G_ID - 10-gigabit ethernet MAC controller ID */
110 /* COMMAND_CONFIG - command and configuration register */
111 #define TGEC_CMD_CFG_EN_TIMESTAMP	0x00100000 /* enable IEEE1588 */
112 #define TGEC_CMD_CFG_TX_ADDR_INS_SEL	0x00080000 /* Tx mac addr w/ second */
116 #define TGEC_CMD_CFG_CMD_FRM_EN		0x00002000 /* CMD frame RX enable */
123 #define TGEC_CMD_CFG_PROM_EN		0x00000010 /* promiscuous mode enable */
124 #define TGEC_CMD_CFG_WAN_MODE		0x00000008 /* WAN mode enable */
125 #define TGEC_CMD_CFG_RX_EN		0x00000002 /* MAC Rx path enable */
126 #define TGEC_CMD_CFG_TX_EN		0x00000001 /* MAC Tx path enable */
129 /* HASHTABLE_CTRL - Hashtable control register */
130 #define HASHTABLE_CTRL_MCAST_EN	0x00000200 /* enable mulitcast Rx hash */
133 /* TX_IPG_LENGTH - Transmit inter-packet gap length register */
136 /* IMASK - interrupt mask register */
141 #define IMASK_TX_ECC_ER		0x00001000 /* Tx frame ECC error mask */
142 #define IMASK_TX_FIFO_UNFL	0x00000800 /* Tx FIFO underflow mask */
143 #define IMASK_TX_ER		0x00000200 /* Tx frame error mask */
156 /* IEVENT - interrupt event register */
161 #define IEVENT_TX_ECC_ER	0x00001000 /* Tx frame ECC error */
162 #define IEVENT_TX_FIFO_UNFL	0x00000800 /* Tx FIFO underflow */
163 #define IEVENT_TX_ER		0x00000200 /* Tx frame error */