Lines Matching +full:rx +full:- +full:tx
2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
18 u32 mac_addr_0; /* Lower 32 bits of 48-bit MAC address */
19 u32 mac_addr_1; /* Upper 16 bits of 48-bit MAC address */
26 u32 tx_ipg_length; /* Transmitter inter-packet-gap register */
27 u32 mac_addr_2; /* Lower 32 bits of the 2nd 48-bit MAC addr */
28 u32 mac_addr_3; /* Upper 16 bits of the 2nd 48-bit MAC addr */
34 u32 tx_frame_u; /* Tx frame counter upper */
35 u32 tx_frame_l; /* Tx frame counter lower */
36 u32 rx_frame_u; /* Rx frame counter upper */
37 u32 rx_frame_l; /* Rx frame counter lower */
38 u32 rx_frame_crc_err_u; /* Rx frame check sequence error upper */
39 u32 rx_frame_crc_err_l; /* Rx frame check sequence error lower */
40 u32 rx_align_err_u; /* Rx alignment error upper */
41 u32 rx_align_err_l; /* Rx alignment error lower */
42 u32 tx_pause_frame_u; /* Tx valid pause frame upper */
43 u32 tx_pause_frame_l; /* Tx valid pause frame lower */
44 u32 rx_pause_frame_u; /* Rx valid pause frame upper */
45 u32 rx_pause_frame_l; /* Rx valid pause frame upper */
46 u32 rx_long_err_u; /* Rx too long frame error upper */
47 u32 rx_long_err_l; /* Rx too long frame error lower */
48 u32 rx_frame_err_u; /* Rx frame length error upper */
49 u32 rx_frame_err_l; /* Rx frame length error lower */
50 u32 tx_vlan_u; /* Tx VLAN frame upper */
51 u32 tx_vlan_l; /* Tx VLAN frame lower */
52 u32 rx_vlan_u; /* Rx VLAN frame upper */
53 u32 rx_vlan_l; /* Rx VLAN frame lower */
54 u32 tx_oct_u; /* Tx octets upper */
55 u32 tx_oct_l; /* Tx octets lower */
56 u32 rx_oct_u; /* Rx octets upper */
57 u32 rx_oct_l; /* Rx octets lower */
58 u32 rx_uni_u; /* Rx unicast frame upper */
59 u32 rx_uni_l; /* Rx unicast frame lower */
60 u32 rx_multi_u; /* Rx multicast frame upper */
61 u32 rx_multi_l; /* Rx multicast frame lower */
62 u32 rx_brd_u; /* Rx broadcast frame upper */
63 u32 rx_brd_l; /* Rx broadcast frame lower */
64 u32 tx_frame_err_u; /* Tx frame error upper */
65 u32 tx_frame_err_l; /* Tx frame error lower */
66 u32 tx_uni_u; /* Tx unicast frame upper */
67 u32 tx_uni_l; /* Tx unicast frame lower */
68 u32 tx_multi_u; /* Tx multicast frame upper */
69 u32 tx_multi_l; /* Tx multicast frame lower */
70 u32 tx_brd_u; /* Tx broadcast frame upper */
71 u32 tx_brd_l; /* Tx broadcast frame lower */
72 u32 rx_drop_u; /* Rx dropped packets upper */
73 u32 rx_drop_l; /* Rx dropped packets lower */
74 u32 rx_eoct_u; /* Rx ethernet octets upper */
75 u32 rx_eoct_l; /* Rx ethernet octets lower */
76 u32 rx_pkt_u; /* Rx packets upper */
77 u32 rx_pkt_l; /* Rx packets lower */
80 u32 rx_64_u; /* Rx 64 oct packet upper */
81 u32 rx_64_l; /* Rx 64 oct packet lower */
82 u32 rx_127_u; /* Rx 65 to 127 oct packet upper */
83 u32 rx_127_l; /* Rx 65 to 127 oct packet lower */
84 u32 rx_255_u; /* Rx 128 to 255 oct packet upper */
85 u32 rx_255_l; /* Rx 128 to 255 oct packet lower */
86 u32 rx_511_u; /* Rx 256 to 511 oct packet upper */
87 u32 rx_511_l; /* Rx 256 to 511 oct packet lower */
88 u32 rx_1023_u; /* Rx 512 to 1023 oct packet upper */
89 u32 rx_1023_l; /* Rx 512 to 1023 oct packet lower */
90 u32 rx_1518_u; /* Rx 1024 to 1518 oct packet upper */
91 u32 rx_1518_l; /* Rx 1024 to 1518 oct packet lower */
92 u32 rx_1519_u; /* Rx 1519 to max oct packet upper */
93 u32 rx_1519_l; /* Rx 1519 to max oct packet lower */
100 u32 rx_err_u; /* Rx frame error upper */
101 u32 rx_err_l; /* Rx frame error lower */
105 /* EC10G_ID - 10-gigabit ethernet MAC controller ID */
110 /* COMMAND_CONFIG - command and configuration register */
112 #define TGEC_CMD_CFG_TX_ADDR_INS_SEL 0x00080000 /* Tx mac addr w/ second */
115 #define TGEC_CMD_CFG_RX_ER_DISC 0x00004000 /* Rx err frm discard enb */
116 #define TGEC_CMD_CFG_CMD_FRM_EN 0x00002000 /* CMD frame RX enable */
121 #define TGEC_CMD_CFG_CRC_FWD 0x00000040 /* fwd Rx CRC frames */
122 #define TGEC_CMD_CFG_PAD_EN 0x00000020 /* MAC remove Rx padding */
125 #define TGEC_CMD_CFG_RX_EN 0x00000002 /* MAC Rx path enable */
126 #define TGEC_CMD_CFG_TX_EN 0x00000001 /* MAC Tx path enable */
129 /* HASHTABLE_CTRL - Hashtable control register */
130 #define HASHTABLE_CTRL_MCAST_EN 0x00000200 /* enable mulitcast Rx hash */
133 /* TX_IPG_LENGTH - Transmit inter-packet gap length register */
136 /* IMASK - interrupt mask register */
141 #define IMASK_TX_ECC_ER 0x00001000 /* Tx frame ECC error mask */
142 #define IMASK_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow mask */
143 #define IMASK_TX_ER 0x00000200 /* Tx frame error mask */
144 #define IMASK_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow mask */
145 #define IMASK_RX_ECC_ER 0x00000080 /* Rx frame ECC error mask */
146 #define IMASK_RX_JAB_FRM 0x00000040 /* Rx jabber frame mask */
147 #define IMASK_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame mask */
148 #define IMASK_RX_RUNT_FRM 0x00000010 /* Rx runt frame mask */
149 #define IMASK_RX_FRAG_FRM 0x00000008 /* Rx fragment frame mask */
150 #define IMASK_RX_LEN_ER 0x00000004 /* Rx payload length error mask */
151 #define IMASK_RX_CRC_ER 0x00000002 /* Rx CRC error mask */
152 #define IMASK_RX_ALIGN_ER 0x00000001 /* Rx alignment error mask */
156 /* IEVENT - interrupt event register */
161 #define IEVENT_TX_ECC_ER 0x00001000 /* Tx frame ECC error */
162 #define IEVENT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */
163 #define IEVENT_TX_ER 0x00000200 /* Tx frame error */
164 #define IEVENT_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow */
165 #define IEVENT_RX_ECC_ER 0x00000080 /* Rx frame ECC error */
166 #define IEVENT_RX_JAB_FRM 0x00000040 /* Rx jabber frame */
167 #define IEVENT_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame */
168 #define IEVENT_RX_RUNT_FRM 0x00000010 /* Rx runt frame */
169 #define IEVENT_RX_FRAG_FRM 0x00000008 /* Rx fragment frame */
170 #define IEVENT_RX_LEN_ER 0x00000004 /* Rx payload length error */
171 #define IEVENT_RX_CRC_ER 0x00000002 /* Rx CRC error */
172 #define IEVENT_RX_ALIGN_ER 0x00000001 /* Rx alignment error */