Lines Matching +full:ram +full:- +full:code

2  * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
5  * based on source code of Shlomi Gridish
7  * SPDX-License-Identifier:	GPL-2.0+
22 #define QE_DATAONLY_SIZE	(QE_MURAM_SIZE - QE_DATAONLY_BASE)
75 /* QE CECR Sub Block Code - sub block code of QE command.
109 /* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command.
220 #define QE_CP_CERCR_MEE		0x8000	/* Multi-user RAM ECC enable */
221 #define QE_CP_CERCR_IEE		0x4000	/* Instruction RAM ECC enable */
222 #define QE_CP_CERCR_CIR		0x0800	/* Common instruction RAM */
224 /* I-RAM */
239 	u8 id[62];		/* Null-terminated identifier string */
240 	u8 split;		/* 0 = shared I-RAM, 1 = split I-RAM */
252 		u8 id[32];	/* Null-terminated identifier */
255 		u32 iram_offset;/* Offset into I-RAM for the code */
256 		u32 count;	/* Number of 32-bit words of the code */