Lines Matching +full:0 +full:x0f000000
18 #define FSL_IFC_V1_1_0 0x01010000
19 #define FSL_IFC_V2_0_0 0x02000000
39 #define CSPR_BA 0xFFFF0000
41 #define CSPR_PORT_SIZE 0x00000180
44 #define CSPR_PORT_SIZE_8 0x00000080
46 #define CSPR_PORT_SIZE_16 0x00000100
48 #define CSPR_PORT_SIZE_32 0x00000180
50 #define CSPR_WP 0x00000040
53 #define CSPR_MSEL 0x00000006
56 #define CSPR_MSEL_NOR 0x00000000
58 #define CSPR_MSEL_NAND 0x00000002
60 #define CSPR_MSEL_GPCM 0x00000004
62 #define CSPR_V 0x00000001
63 #define CSPR_V_SHIFT 0
66 #define CSPR_PHYS_ADDR(x) (((uint64_t)x) & 0xffff0000)
71 #define IFC_AMASK_MASK 0xFFFF0000
80 #define CSOR_NAND_ECC_ENC_EN 0x80000000
81 #define CSOR_NAND_ECC_MODE_MASK 0x30000000
83 #define CSOR_NAND_ECC_MODE_4 0x00000000
85 #define CSOR_NAND_ECC_MODE_8 0x10000000
87 #define CSOR_NAND_ECC_DEC_EN 0x04000000
89 #define CSOR_NAND_RAL_MASK 0x01800000
91 #define CSOR_NAND_RAL_1 0x00000000
92 #define CSOR_NAND_RAL_2 0x00800000
93 #define CSOR_NAND_RAL_3 0x01000000
94 #define CSOR_NAND_RAL_4 0x01800000
96 #define CSOR_NAND_PGS_MASK 0x00180000
98 #define CSOR_NAND_PGS_512 0x00000000
99 #define CSOR_NAND_PGS_2K 0x00080000
100 #define CSOR_NAND_PGS_4K 0x00100000
101 #define CSOR_NAND_PGS_8K 0x00180000
103 #define CSOR_NAND_SPRZ_MASK 0x0000E000
105 #define CSOR_NAND_SPRZ_16 0x00000000
106 #define CSOR_NAND_SPRZ_64 0x00002000
107 #define CSOR_NAND_SPRZ_128 0x00004000
108 #define CSOR_NAND_SPRZ_210 0x00006000
109 #define CSOR_NAND_SPRZ_218 0x00008000
110 #define CSOR_NAND_SPRZ_224 0x0000A000
111 #define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000
113 #define CSOR_NAND_PB_MASK 0x00000700
117 #define CSOR_NAND_TRHZ_MASK 0x0000001C
119 #define CSOR_NAND_TRHZ_20 0x00000000
120 #define CSOR_NAND_TRHZ_40 0x00000004
121 #define CSOR_NAND_TRHZ_60 0x00000008
122 #define CSOR_NAND_TRHZ_80 0x0000000C
123 #define CSOR_NAND_TRHZ_100 0x00000010
125 #define CSOR_NAND_BCTLD 0x00000001
131 #define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000
133 #define CSOR_NOR_PGRD_EN 0x10000000
135 #define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000
137 #define CSOR_NOR_ADM_MASK 0x0003E000
141 #define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000
142 #define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020
144 #define CSOR_NOR_TRHZ_MASK 0x0000001C
146 #define CSOR_NOR_TRHZ_20 0x00000000
147 #define CSOR_NOR_TRHZ_40 0x00000004
148 #define CSOR_NOR_TRHZ_60 0x00000008
149 #define CSOR_NOR_TRHZ_80 0x0000000C
150 #define CSOR_NOR_TRHZ_100 0x00000010
152 #define CSOR_NOR_BCTLD 0x00000001
158 #define CSOR_GPCM_GPMODE_NORMAL 0x00000000
160 #define CSOR_GPCM_GPMODE_ASIC 0x80000000
162 #define CSOR_GPCM_PARITY_EVEN 0x40000000
164 #define CSOR_GPCM_PAR_EN 0x20000000
166 #define CSOR_GPCM_GPTO_MASK 0x0F000000
170 #define CSOR_GPCM_RGETA_EXT 0x00080000
172 #define CSOR_GPCM_WGETA_EXT 0x00040000
174 #define CSOR_GPCM_ADM_MASK 0x0003E000
178 #define CSOR_GPCM_GAPERRD_MASK 0x00000180
182 #define CSOR_GPCM_TRHZ_MASK 0x0000001C
183 #define CSOR_GPCM_TRHZ_20 0x00000000
184 #define CSOR_GPCM_TRHZ_40 0x00000004
185 #define CSOR_GPCM_TRHZ_60 0x00000008
186 #define CSOR_GPCM_TRHZ_80 0x0000000C
187 #define CSOR_GPCM_TRHZ_100 0x00000010
189 #define CSOR_GPCM_BCTLD 0x00000001
197 #define FTIM0_NAND 0x7EFF3F3F
204 #define FTIM0_NAND_TWH_SHIFT 0
209 #define FTIM1_NAND 0xFFFF3FFF
216 #define FTIM1_NAND_TRP_SHIFT 0
221 #define FTIM2_NAND 0x1FE1F8FF
226 #define FTIM2_NAND_TWHRE_SHIFT 0
231 #define FTIM3_NAND 0xFF000000
238 #define FTIM0_NOR 0xF03F3F3F
245 #define FTIM0_NOR_TEAHC_SHIFT 0
250 #define FTIM1_NOR 0xFF003F3F
255 #define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0
260 #define FTIM2_NOR 0x0F3CFCFF
267 #define FTIM2_NOR_TWP_SHIFT 0
273 #define FTIM0_GPCM 0xF03F3F3F
280 #define FTIM0_GPCM_TEAHC_SHIFT 0
285 #define FTIM1_GPCM 0xFF003F00
293 #define FTIM2_GPCM 0x0F3C00FF
298 #define FTIM2_GPCM_TWP_SHIFT 0
305 #define IFC_RB_STAT_READY_CS0 0x80000000
306 #define IFC_RB_STAT_READY_CS1 0x40000000
307 #define IFC_RB_STAT_READY_CS2 0x20000000
308 #define IFC_RB_STAT_READY_CS3 0x10000000
313 #define IFC_GCR_MASK 0x8000F800
315 #define IFC_GCR_SOFT_RST_ALL 0x80000000
317 #define IFC_GCR_TBCTL_TRN_TIME 0x0000F800
324 #define IFC_CM_EVTER_STAT_CSER 0x80000000
330 #define IFC_CM_EVTER_EN_CSEREN 0x80000000
336 #define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000
339 * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
342 #define IFC_CM_ERATTR0_ERTYP_READ 0x80000000
343 #define IFC_CM_ERATTR0_ERAID 0x0FF00000
344 #define IFC_CM_ERATTR0_ESRCID 0x0000FF00
349 #define IFC_CCR_MASK 0x0F0F8800
351 #define IFC_CCR_CLK_DIV_MASK 0x0F000000
355 #define IFC_CCR_CLK_DLY_MASK 0x000F0000
359 #define IFC_CCR_INV_CLK_EN 0x00008000
361 #define IFC_CCR_FB_IFC_CLK_SEL 0x00000800
367 #define IFC_CSR_CLK_STAT_STABLE 0x80000000
376 #define IFC_NAND_NCFGR_BOOT 0x80000000
378 #define IFC_NAND_SRAM_INIT_EN 0x20000000
380 #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
382 #define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000
384 #define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000
388 #define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF
389 #define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0
395 #define IFC_NAND_FCR0_CMD0 0xFF000000
397 #define IFC_NAND_FCR0_CMD1 0x00FF0000
399 #define IFC_NAND_FCR0_CMD2 0x0000FF00
401 #define IFC_NAND_FCR0_CMD3 0x000000FF
402 #define IFC_NAND_FCR0_CMD3_SHIFT 0
403 #define IFC_NAND_FCR1_CMD4 0xFF000000
405 #define IFC_NAND_FCR1_CMD5 0x00FF0000
407 #define IFC_NAND_FCR1_CMD6 0x0000FF00
409 #define IFC_NAND_FCR1_CMD7 0x000000FF
410 #define IFC_NAND_FCR1_CMD7_SHIFT 0
416 #define IFC_NAND_COL_MS 0x80000000
418 #define IFC_NAND_COL_CA_MASK 0x00000FFF
424 #define IFC_NAND_BC 0x000001FF
430 #define IFC_NAND_FIR0_OP0 0xFC000000
432 #define IFC_NAND_FIR0_OP1 0x03F00000
434 #define IFC_NAND_FIR0_OP2 0x000FC000
436 #define IFC_NAND_FIR0_OP3 0x00003F00
438 #define IFC_NAND_FIR0_OP4 0x000000FC
440 #define IFC_NAND_FIR1_OP5 0xFC000000
442 #define IFC_NAND_FIR1_OP6 0x03F00000
444 #define IFC_NAND_FIR1_OP7 0x000FC000
446 #define IFC_NAND_FIR1_OP8 0x00003F00
448 #define IFC_NAND_FIR1_OP9 0x000000FC
450 #define IFC_NAND_FIR2_OP10 0xFC000000
452 #define IFC_NAND_FIR2_OP11 0x03F00000
454 #define IFC_NAND_FIR2_OP12 0x000FC000
456 #define IFC_NAND_FIR2_OP13 0x00003F00
458 #define IFC_NAND_FIR2_OP14 0x000000FC
505 #define IFC_NAND_CSEL 0x0C000000
507 #define IFC_NAND_CSEL_CS0 0x00000000
508 #define IFC_NAND_CSEL_CS1 0x04000000
509 #define IFC_NAND_CSEL_CS2 0x08000000
510 #define IFC_NAND_CSEL_CS3 0x0C000000
516 #define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000
518 #define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000
520 #define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000
522 #define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000
524 #define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000
526 #define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800
532 #define IFC_NAND_EVTER_STAT_OPC 0x80000000
534 #define IFC_NAND_EVTER_STAT_FTOER 0x08000000
536 #define IFC_NAND_EVTER_STAT_WPER 0x04000000
538 #define IFC_NAND_EVTER_STAT_ECCER 0x02000000
540 #define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000
542 #define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000
544 #define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800
550 #define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000
551 /* Small Page 0-15 Done */
553 /* Large Page(2K) 0-3 Done */
554 #define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4))
555 /* Large Page(4K) 0-1 Done */
556 #define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8))
562 #define IFC_NAND_EVTER_EN_OPC_EN 0x80000000
564 #define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000
566 #define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000
568 #define IFC_NAND_EVTER_EN_WPER_EN 0x04000000
570 #define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000
576 #define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000
578 #define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000
580 #define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000
582 #define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000
584 #define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000
587 * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
589 #define IFC_NAND_ERATTR0_MASK 0x0C080000
591 #define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000
592 #define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000
593 #define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000
594 #define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000
596 #define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000
602 #define IFC_NAND_NFSR_RS0 0xFF000000
604 #define IFC_NAND_NFSR_RS1 0x00FF0000
609 /* Number of ECC errors on sector n (n = 0-15) */
610 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000
612 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000
614 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00
616 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F
617 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0
618 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000
620 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000
622 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00
624 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F
625 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0
626 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000
628 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000
630 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00
632 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F
633 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0
634 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000
636 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000
638 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00
640 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F
641 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0
646 #define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000
654 #define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000
656 #define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000
662 #define IFC_NAND_MDR_RDATA0 0xFF000000
664 #define IFC_NAND_MDR_RDATA1 0x00FF0000
673 #define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000
675 #define IFC_NOR_EVTER_STAT_WPER 0x04000000
677 #define IFC_NOR_EVTER_STAT_STOER 0x01000000
683 #define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000
685 #define IFC_NOR_EVTER_EN_WPEREN 0x04000000
687 #define IFC_NOR_EVTER_EN_STOEREN 0x01000000
693 #define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000
695 #define IFC_NOR_EVTER_INTR_WPEREN 0x04000000
697 #define IFC_NOR_EVTER_INTR_STOEREN 0x01000000
700 * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
703 #define IFC_NOR_ERATTR0_ERSRCID 0xFF000000
705 #define IFC_NOR_ERATTR0_ERAID 0x000FF000
707 #define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000
708 #define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010
709 #define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020
710 #define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030
712 #define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001
717 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000
718 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00
723 #define IFC_NORCR_MASK 0x0F0F0000
725 #define IFC_NORCR_NUM_PHASE_MASK 0x0F000000
729 #define IFC_NORCR_STOCNT_MASK 0x000F0000
740 #define IFC_GPCM_EVTER_STAT_TOER 0x04000000
742 #define IFC_GPCM_EVTER_STAT_PER 0x01000000
748 #define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000
750 #define IFC_GPCM_EVTER_EN_PER_EN 0x01000000
756 #define IFC_GPCM_EEIER_TOERIR_EN 0x04000000
758 #define IFC_GPCM_EEIER_PERIR_EN 0x01000000
761 * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
764 #define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000
766 #define IFC_GPCM_ERATTR0_ERAID 0x000FF000
768 #define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000
769 #define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040
770 #define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080
771 #define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0
773 #define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001
779 #define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00
781 #define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0
783 #define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001
788 #define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */
852 u32 res1[0x4];
855 u32 res2[0x8];
871 u32 res10[0x24];
877 u32 res12[0x10];
885 u32 res16[0x2];
887 u32 res17[0x2];
893 u32 res19[0x10];
895 u32 res20[0x1];
897 u32 res21[0x1c];
899 u32 res22[0x2];
903 u32 res24[0x1c];
908 u32 res26[0x3C];
916 u32 res1[0x2];
918 u32 res2[0x2];
920 u32 res3[0x2];
924 u32 res4[0x4];
926 u32 res5[0xEF];
934 u32 res1[0x2];
936 u32 res2[0x2];
938 u32 res3[0x2];
975 u32 res[0x2];
986 u32 res[0x8];
996 u32 res1[0x2];
1009 u32 res7[0x2];
1011 u32 res8[0x2];
1013 u32 res9[0x2];
1015 u32 res10[0x2];
1018 u32 res11[0x2];