u-boot/include/fsl_fman.h

4  * Copyright 2010-2011 Freescale Semiconductor, Inc.
6  * SPDX-License-Identifier:	GPL-2.0+
70 	u32 fmbm_rcfg;	/* Rx configuration */
71 	u32 fmbm_rst;	/* Rx status */
72 	u32 fmbm_rda;	/* Rx DMA attributes */
73 	u32 fmbm_rfp;	/* Rx FIFO parameters */
74 	u32 fmbm_rfed;	/* Rx frame end data */
75 	u32 fmbm_ricp;	/* Rx internal context parameters */
76 	u32 fmbm_rim;	/* Rx internal margins */
77 	u32 fmbm_rebm;	/* Rx external buffer margins */
78 	u32 fmbm_rfne;	/* Rx frame next engine */
79 	u32 fmbm_rfca;	/* Rx frame command attributes */
80 	u32 fmbm_rfpne;	/* Rx frame parser next engine */
81 	u32 fmbm_rpso;	/* Rx parse start offset */
82 	u32 fmbm_rpp;	/* Rx policer profile */
83 	u32 fmbm_rccb;	/* Rx coarse classification base */
85 	u32 fmbm_rprai[0x8];	/* Rx parse results array Initialization */
86 	u32 fmbm_rfqid;		/* Rx frame queue ID */
87 	u32 fmbm_refqid;	/* Rx error frame queue ID */
88 	u32 fmbm_rfsdm;		/* Rx frame status discard mask */
89 	u32 fmbm_rfsem;		/* Rx frame status error mask */
90 	u32 fmbm_rfene;		/* Rx frame enqueue next engine */
98 	u32 fmbm_rstc;		/* Rx statistics counters */
99 	u32 fmbm_rfrc;		/* Rx frame counters */
100 	u32 fmbm_rfbc;		/* Rx bad frames counter */
101 	u32 fmbm_rlfc;		/* Rx large frames counter */
102 	u32 fmbm_rffc;		/* Rx filter frames counter */
103 	u32 fmbm_rfdc;		/* Rx frame discard counter */
104 	u32 fmbm_rfldec;	/* Rx frames list DMA error counter */
105 	u32 fmbm_rodc;		/* Rx out of buffers discard counter */
106 	u32 fmbm_rbdc;		/* Rx buffers deallocate counter */
108 	u32 fmbm_rpc;		/* Rx performance counters */
109 	u32 fmbm_rpcp;		/* Rx performance count parameters */
110 	u32 fmbm_rccn;		/* Rx cycle counter */
111 	u32 fmbm_rtuc;		/* Rx tasks utilization counter */
112 	u32 fmbm_rrquc;		/* Rx receive queue utilization counter */
113 	u32 fmbm_rduc;		/* Rx DMA utilization counter */
114 	u32 fmbm_rfuc;		/* Rx FIFO utilization counter */
115 	u32 fmbm_rpac;		/* Rx pause activation counter */
117 	u32 fmbm_rdbg;		/* Rx debug configuration */
120 /* FMBM_RCFG - Rx configuration */
125 /* FMBM_RST - Rx status */
126 #define FMBM_RST_BSY		0x80000000 /* Rx port is busy */
128 /* FMBM_RFCA - Rx frame command attributes */
133 /* FMBM_RSTC - Rx statistics */
137 	u32 fmbm_tcfg;	/* Tx configuration */
138 	u32 fmbm_tst;	/* Tx status */
139 	u32 fmbm_tda;	/* Tx DMA attributes */
140 	u32 fmbm_tfp;	/* Tx FIFO parameters */
141 	u32 fmbm_tfed;	/* Tx frame end data */
142 	u32 fmbm_ticp;	/* Tx internal context parameters */
143 	u32 fmbm_tfne;	/* Tx frame next engine */
144 	u32 fmbm_tfca;	/* Tx frame command attributes */
145 	u32 fmbm_tcfqid;/* Tx confirmation frame queue ID */
146 	u32 fmbm_tfeqid;/* Tx error frame queue ID */
147 	u32 fmbm_tfene;	/* Tx frame enqueue next engine */
148 	u32 fmbm_trlmts;/* Tx rate limiter scale */
149 	u32 fmbm_trlmt;	/* Tx rate limiter */
151 	u32 fmbm_tstc;	/* Tx statistics counters */
152 	u32 fmbm_tfrc;	/* Tx frame counter */
153 	u32 fmbm_tfdc;	/* Tx frames discard counter */
154 	u32 fmbm_tfledc;/* Tx frame length error discard counter */
155 	u32 fmbm_tfufdc;/* Tx frame unsupported format discard counter */
156 	u32 fmbm_tbdc;	/* Tx buffers deallocate counter */
158 	u32 fmbm_tpc;	/* Tx performance counters */
159 	u32 fmbm_tpcp;	/* Tx performance count parameters */
160 	u32 fmbm_tccn;	/* Tx cycle counter */
161 	u32 fmbm_ttuc;	/* Tx tasks utilization counter */
162 	u32 fmbm_ttcquc;/* Tx transmit confirm queue utilization counter */
163 	u32 fmbm_tduc;	/* Tx DMA utilization counter */
164 	u32 fmbm_tfuc;	/* Tx FIFO utilization counter */
166 	u32 fmbm_tdcfg;	/* Tx debug configuration */
169 /* FMBM_TCFG - Tx configuration */
173 /* FMBM_TST - Tx status */
174 #define FMBM_TST_BSY		0x80000000 /* Tx port is busy */
176 /* FMBM_TFCA - Tx frame command attributes */
181 /* FMBM_TSTC - Tx statistics counters */
184 /* FMBM_INIT - BMI initialization register */
187 /* FMBM_CFG1 - BMI configuration 1 */
192 /* FMBM_IEVR - interrupt event */
198 /* FMBM_IER - interrupt enable */
205 /* FMBM_PP - BMI Port Parameters */
207 #define FMBM_PP_MXT(x)		(((x-1) << 24) & FMBM_PP_MXT_MASK)
209 #define FMBM_PP_MXD(x)		(((x-1) << 8) & FMBM_PP_MXD_MASK)
211 /* FMBM_PFS - BMI Port FIFO Size */
215 /* FMQM_GC - global configuration */
224 /* FMQM_EIE - error interrupt event register */
225 #define FMQM_EIE_DEE		0x80000000 /* double-bit ECC error */
229 /* FMQM_EIEN - error interrupt enable register */
230 #define FMQM_EIEN_DEEN		0x80000000 /* double-bit ECC error */
234 /* FMQM_IE - interrupt event register */
235 #define FMQM_IE_SEE		0x80000000 /* single-bit ECC error detected */
238 /* FMQM_IEN - interrupt enable register */
239 #define FMQM_IEN_SEE		0x80000000 /* single-bit ECC err IRQ enable */
242 /* NIA - next invoked action */
248 #define NIA_RISC_AC_IM_TX	0x00000008 /* independent mode Tx */
249 #define NIA_RISC_AC_IM_RX	0x0000000a /* independent mode Rx */
279 	u32	fmdmplr[32];	/* FM DMA PID-LIODN # register */
283 /* FMDMSR - Fman DMA status register */
301 /* FMDMMR - FMan DMA mode register */
313 	u32	fpmfcevent[0x4];/* FMan controller event 0-3 */
315 	u32	fpmfcmask[0x4];	/* FMan controller mask 0-3 */
323 	u32	fpmdrd[0x4];	/* data_ram data 0-3 */
333 	u32	fpmcev[0x4];	/* CPU event 0-3 */
341 /* FMFP_PRC - FPM Port_ID Control Register */
352 /* FMFP_EE - FPM event and enable register */
369 /* FMFP_RCR - FMan Rams Control and Event */
399 	u8	res1[0x1000 - 0x138];