Lines Matching +full:inter +full:- +full:data

2  * Copyright 2009-2011 Freescale Semiconductor, Inc.
4  * SPDX-License-Identifier:	GPL-2.0+
31 	u32	ipgifg;		/* inter-packet/inter-frame gap */
32 	u32	hafdup;		/* half-duplex control */
122 /* IEVENT - interrupt events register */
137 #define IEVENT_TDPE	0x00000002 /* Internal data parity error on Tx */
138 #define IEVENT_RDPE	0x00000001 /* Internal data parity error on Rx */
142 /* IMASK - interrupt mask register */
157 #define IMASK_TDPEEN	0x00000002 /* Internal data parity error on Tx enable */
158 #define IMASK_RDPEEN	0x00000001 /* Internal data parity error on Rx enable */
162 /* ECNTRL - ethernet control register */
167 #define ECNTRL_GMIIM	0x00000040 /* 1- GMII or RGMII interface mode */
168 #define ECNTRL_TBIM	0x00000020 /* 1- Ten-bit interface mode */
169 #define ECNTRL_RPM	0x00000010 /* 1- RGMII reduced-pin mode */
170 #define ECNTRL_R100M	0x00000008 /* 1- RGMII 100 Mbps, SGMII 100 Mbps
171 				      0- RGMII 10 Mbps, SGMII 10 Mbps */
172 #define ECNTRL_SGMIIM	0x00000002 /* 1- SGMII interface mode */
173 #define ECNTRL_TBIM	0x00000020 /* 1- TBI Interface mode (for SGMII) */
177 /* TCTRL - Transmit control register */
178 #define TCTRL_THDF	0x00000800 /* Transmit half-duplex flow control */
179 #define TCTRL_TTSE	0x00000040 /* Transmit time-stamp enable */
183 /* RCTRL - Receive control register */
188 #define RCTRL_RTSE	0x00000040 /* receive 1588 time-stamp enable */
196 /* MACCFG1 - MAC configuration 1 register */
211 /* MACCFG2 - MAC configuration 2 register */