Lines Matching defs:dtsec
12 struct dtsec { struct
13 u32 tsec_id; /* controller ID and version */
14 u32 tsec_id2; /* controller ID and configuration */
15 u32 ievent; /* interrupt event */
16 u32 imask; /* interrupt mask */
17 u32 res0;
18 u32 ecntrl; /* ethernet control and configuration */
19 u32 ptv; /* pause time value */
20 u32 tbipa; /* TBI PHY address */
21 u32 res1[8];
22 u32 tctrl; /* Transmit control register */
23 u32 res2[3];
24 u32 rctrl; /* Receive control register */
25 u32 res3[11];
26 u32 igaddr[8]; /* Individual group address */
27 u32 gaddr[8]; /* group address */
28 u32 res4[16];
29 u32 maccfg1; /* MAC configuration register 1 */
30 u32 maccfg2; /* MAC configuration register 2 */
31 u32 ipgifg; /* inter-packet/inter-frame gap */
32 u32 hafdup; /* half-duplex control */
33 u32 maxfrm; /* Maximum frame size */
34 u32 res5[3];
35 u32 miimcfg; /* MII management configuration */
36 u32 miimcom; /* MII management command */
37 u32 miimadd; /* MII management address */
38 u32 miimcon; /* MII management control */
39 u32 miimstat; /* MII management status */
40 u32 miimind; /* MII management indicator */
41 u32 res6;
42 u32 ifstat; /* Interface status */
43 u32 macstnaddr1; /* MAC station address 1 */
44 u32 macstnaddr2; /* MAC station address 2 */
45 u32 res7[46];
47 u32 tr64; /* Tx and Rx 64 bytes frame */
48 u32 tr127; /* Tx and Rx 65 to 127 bytes frame */
49 u32 tr255; /* Tx and Rx 128 to 255 bytes frame */
50 u32 tr511; /* Tx and Rx 256 to 511 bytes frame */
51 u32 tr1k; /* Tx and Rx 512 to 1023 bytes frame */
52 u32 trmax; /* Tx and Rx 1024 to 1518 bytes frame */
53 u32 trmgv; /* Tx and Rx 1519 to 1522 good VLAN frame */
55 u32 rbyt; /* Receive byte counter */
56 u32 rpkt; /* Receive packet counter */
57 u32 rfcs; /* Receive FCS error */
58 u32 rmca; /* Receive multicast packet */
59 u32 rbca; /* Receive broadcast packet */
60 u32 rxcf; /* Receive control frame */
61 u32 rxpf; /* Receive pause frame */
62 u32 rxuo; /* Receive unknown OP code */
63 u32 raln; /* Receive alignment error */
64 u32 rflr; /* Receive frame length error */
65 u32 rcde; /* Receive code error */
66 u32 rcse; /* Receive carrier sense error */
67 u32 rund; /* Receive undersize packet */
68 u32 rovr; /* Receive oversize packet */
69 u32 rfrg; /* Receive fragments counter */
70 u32 rjbr; /* Receive jabber counter */
71 u32 rdrp; /* Receive drop counter */
73 u32 tbyt; /* Transmit byte counter */
74 u32 tpkt; /* Transmit packet */
75 u32 tmca; /* Transmit multicast packet */
76 u32 tbca; /* Transmit broadcast packet */
77 u32 txpf; /* Transmit pause control frame */
78 u32 tdfr; /* Transmit deferral packet */
79 u32 tedf; /* Transmit excessive deferral pkt */
80 u32 tscl; /* Transmit single collision pkt */
81 u32 tmcl; /* Transmit multiple collision pkt */
82 u32 tlcl; /* Transmit late collision pkt */
83 u32 txcl; /* Transmit excessive collision */
84 u32 tncl; /* Transmit total collision */
85 u32 res8;
86 u32 tdrp; /* Transmit drop frame */
87 u32 tjbr; /* Transmit jabber frame */
88 u32 tfcs; /* Transmit FCS error */
89 u32 txcf; /* Transmit control frame */
90 u32 tovr; /* Transmit oversize frame */
91 u32 tund; /* Transmit undersize frame */
92 u32 tfrg; /* Transmit fragments frame */
94 u32 car1; /* carry register 1 */
95 u32 car2; /* carry register 2 */
96 u32 cam1; /* carry register 1 mask */
97 u32 cam2; /* carry register 2 mask */
98 u32 res9[80];