Lines Matching +full:0 +full:x07000000
27 #define DDR3_RTT_OFF 0
34 #define DDR4_RTT_OFF 0
43 #define DDR2_RTT_OFF 0
73 #define FSL_DDR_ODT_NEVER 0x0
74 #define FSL_DDR_ODT_CS 0x1
75 #define FSL_DDR_ODT_ALL_OTHER_CS 0x2
76 #define FSL_DDR_ODT_OTHER_DIMM 0x3
77 #define FSL_DDR_ODT_ALL 0x4
78 #define FSL_DDR_ODT_SAME_DIMM 0x5
79 #define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6
80 #define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7
83 #define FSL_DDR_CS0_CS1 0x40
84 #define FSL_DDR_CS2_CS3 0x20
86 #define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
89 #define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0
90 #define FSL_DDR_PAGE_INTERLEAVING 0x1
91 #define FSL_DDR_BANK_INTERLEAVING 0x2
92 #define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
93 #define FSL_DDR_256B_INTERLEAVING 0x8
94 #define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA
95 #define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC
96 #define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD
98 #define FSL_DDR_4WAY_1KB_INTERLEAVING 0x1A
99 #define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C
100 #define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D
102 #define SDRAM_CS_CONFIG_EN 0x80000000
106 #define SDRAM_CFG_MEM_EN 0x80000000
107 #define SDRAM_CFG_SREN 0x40000000
108 #define SDRAM_CFG_ECC_EN 0x20000000
109 #define SDRAM_CFG_RD_EN 0x10000000
110 #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
111 #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
112 #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
114 #define SDRAM_CFG_DYN_PWR 0x00200000
115 #define SDRAM_CFG_DBW_MASK 0x00180000
117 #define SDRAM_CFG_32_BE 0x00080000
118 #define SDRAM_CFG_16_BE 0x00100000
119 #define SDRAM_CFG_8_BE 0x00040000
120 #define SDRAM_CFG_NCAP 0x00020000
121 #define SDRAM_CFG_2T_EN 0x00008000
122 #define SDRAM_CFG_BI 0x00000001
124 #define SDRAM_CFG2_FRC_SR 0x80000000
125 #define SDRAM_CFG2_D_INIT 0x00000010
126 #define SDRAM_CFG2_AP_EN 0x00000020
127 #define SDRAM_CFG2_ODT_CFG_MASK 0x00600000
128 #define SDRAM_CFG2_ODT_NEVER 0
133 #define SDRAM_INTERVAL_BSTOPRE 0x3FFF
134 #define TIMING_CFG_2_CPO_MASK 0x0F800000
138 #define RD_TO_PRE_MASK 0xf
140 #define WR_DATA_DELAY_MASK 0xf
143 #define RD_TO_PRE_MASK 0x7
145 #define WR_DATA_DELAY_MASK 0x7
150 #define DDR_EOR_RD_REOD_DIS 0x07000000
151 #define DDR_EOR_WD_REOD_DIS 0x00100000
154 #define MD_CNTL_MD_EN 0x80000000
155 #define MD_CNTL_CS_SEL_CS0 0x00000000
156 #define MD_CNTL_CS_SEL_CS1 0x10000000
157 #define MD_CNTL_CS_SEL_CS2 0x20000000
158 #define MD_CNTL_CS_SEL_CS3 0x30000000
159 #define MD_CNTL_CS_SEL_CS0_CS1 0x40000000
160 #define MD_CNTL_CS_SEL_CS2_CS3 0x50000000
161 #define MD_CNTL_MD_SEL_MR 0x00000000
162 #define MD_CNTL_MD_SEL_EMR 0x01000000
163 #define MD_CNTL_MD_SEL_EMR2 0x02000000
164 #define MD_CNTL_MD_SEL_EMR3 0x03000000
165 #define MD_CNTL_SET_REF 0x00800000
166 #define MD_CNTL_SET_PRE 0x00400000
167 #define MD_CNTL_CKE_CNTL_LOW 0x00100000
168 #define MD_CNTL_CKE_CNTL_HIGH 0x00200000
169 #define MD_CNTL_WRCW 0x00080000
170 #define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF)
171 #define MD_CNTL_CS_SEL(x) (((x) & 0x7) << 28)
172 #define MD_CNTL_MD_SEL(x) (((x) & 0xf) << 24)
175 #define DDR_CDR1_DHC_EN 0x80000000
176 #define DDR_CDR1_V0PT9_EN 0x40000000
178 #define DDR_CDR1_ODT_MASK 0x6
179 #define DDR_CDR2_ODT_MASK 0x1
182 #define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8))
183 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
184 #define DDR_CDR2_VREF_RANGE_2 0x00000040
190 #define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */
191 #define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */
194 #define DDR_CAS_TO_PRE_SUB_MASK 0x0000f000 /* CAS to preamble subtract value */
204 #define DDR_CDR_ODT_OFF 0x0
205 #define DDR_CDR_ODT_120ohm 0x1
206 #define DDR_CDR_ODT_200ohm 0x2
207 #define DDR_CDR_ODT_75ohm 0x3
208 #define DDR_CDR_ODT_60ohm 0x5
209 #define DDR_CDR_ODT_46ohm 0x7
211 #define DDR_CDR_ODT_OFF 0x0
212 #define DDR_CDR_ODT_100ohm 0x1
213 #define DDR_CDR_ODT_120OHM 0x2
214 #define DDR_CDR_ODT_80ohm 0x3
215 #define DDR_CDR_ODT_60ohm 0x4
216 #define DDR_CDR_ODT_40ohm 0x5
217 #define DDR_CDR_ODT_50ohm 0x6
218 #define DDR_CDR_ODT_30ohm 0x7
220 #define DDR_CDR_ODT_OFF 0x0
221 #define DDR_CDR_ODT_120ohm 0x1
222 #define DDR_CDR_ODT_180ohm 0x2
223 #define DDR_CDR_ODT_75ohm 0x3
224 #define DDR_CDR_ODT_110ohm 0x4
225 #define DDR_CDR_ODT_60hm 0x5
226 #define DDR_CDR_ODT_70ohm 0x6
227 #define DDR_CDR_ODT_47ohm 0x7
230 #define DDR_CDR_ODT_75ohm 0x0
231 #define DDR_CDR_ODT_55ohm 0x1
232 #define DDR_CDR_ODT_60ohm 0x2
233 #define DDR_CDR_ODT_50ohm 0x3
234 #define DDR_CDR_ODT_150ohm 0x4
235 #define DDR_CDR_ODT_43ohm 0x5
236 #define DDR_CDR_ODT_120ohm 0x6
316 #define DDR_DATA_BUS_WIDTH_64 0
319 #define DDR_CSWL_CS0 0x04000001
450 return 0; in __board_need_mem_reset()
484 * @return 0 if OK, -ve on error