Lines Matching +full:0 +full:x00000067
438 #define SCMI_PCLK_KEYREADER 0
472 // CRU_SOFTRST_CON03(Offset:0xA0C)
473 #define SRST_NCOREPORESET0 0x00000030
474 #define SRST_NCOREPORESET1 0x00000031
475 #define SRST_NCOREPORESET2 0x00000032
476 #define SRST_NCOREPORESET3 0x00000033
477 #define SRST_NCORESET0 0x00000034
478 #define SRST_NCORESET1 0x00000035
479 #define SRST_NCORESET2 0x00000036
480 #define SRST_NCORESET3 0x00000037
481 #define SRST_NL2RESET 0x00000038
482 #define SRST_ARESETN_M_CORE_BIU 0x00000039
483 #define SRST_RESETN_CORE_CRYPTO 0x0000003A
485 // CRU_SOFTRST_CON05(Offset:0xA14)
486 #define SRST_PRESETN_DBG 0x0000005D
487 #define SRST_POTRESETN_DBG 0x0000005E
488 #define SRST_NTRESETN_DBG 0x0000005F
490 // CRU_SOFTRST_CON06(Offset:0xA18)
491 #define SRST_PRESETN_CORE_GRF 0x00000062
492 #define SRST_PRESETN_DAPLITE_BIU 0x00000063
493 #define SRST_PRESETN_CPU_BIU 0x00000064
494 #define SRST_RESETN_REF_PVTPLL_CORE 0x00000067
496 // CRU_SOFTRST_CON08(Offset:0xA20)
497 #define SRST_ARESETN_BUS_VOPGL_BIU 0x00000081
498 #define SRST_ARESETN_BUS_H_BIU 0x00000083
499 #define SRST_ARESETN_SYSMEM_BIU 0x00000088
500 #define SRST_ARESETN_BUS_BIU 0x0000008A
501 #define SRST_HRESETN_BUS_BIU 0x0000008B
502 #define SRST_PRESETN_BUS_BIU 0x0000008C
503 #define SRST_PRESETN_DFT2APB 0x0000008D
504 #define SRST_PRESETN_BUS_GRF 0x0000008F
506 // CRU_SOFTRST_CON09(Offset:0xA24)
507 #define SRST_ARESETN_BUS_M_BIU 0x00000090
508 #define SRST_ARESETN_GIC 0x00000091
509 #define SRST_ARESETN_SPINLOCK 0x00000092
510 #define SRST_ARESETN_DMAC 0x00000094
511 #define SRST_PRESETN_TIMER 0x00000095
512 #define SRST_RESETN_TIMER0 0x00000096
513 #define SRST_RESETN_TIMER1 0x00000097
514 #define SRST_RESETN_TIMER2 0x00000098
515 #define SRST_RESETN_TIMER3 0x00000099
516 #define SRST_RESETN_TIMER4 0x0000009A
517 #define SRST_RESETN_TIMER5 0x0000009B
518 #define SRST_PRESETN_JDBCK_DAP 0x0000009C
519 #define SRST_RESETN_JDBCK_DAP 0x0000009D
520 #define SRST_PRESETN_WDT_NS 0x0000009F
522 // CRU_SOFTRST_CON10(Offset:0xA28)
523 #define SRST_TRESETN_WDT_NS 0x000000A0
524 #define SRST_HRESETN_TRNG_NS 0x000000A3
525 #define SRST_PRESETN_UART0 0x000000A7
526 #define SRST_SRESETN_UART0 0x000000A8
527 #define SRST_RESETN_PKA_CRYPTO 0x000000AA
528 #define SRST_ARESETN_CRYPTO 0x000000AB
529 #define SRST_HRESETN_CRYPTO 0x000000AC
530 #define SRST_PRESETN_DMA2DDR 0x000000AD
531 #define SRST_ARESETN_DMA2DDR 0x000000AE
533 // CRU_SOFTRST_CON11(Offset:0xA2C)
534 #define SRST_PRESETN_PWM0 0x000000B4
535 #define SRST_RESETN_PWM0 0x000000B5
536 #define SRST_PRESETN_PWM1 0x000000B7
537 #define SRST_RESETN_PWM1 0x000000B8
538 #define SRST_PRESETN_SCR 0x000000BA
539 #define SRST_ARESETN_DCF 0x000000BB
540 #define SRST_PRESETN_INTMUX 0x000000BC
542 // CRU_SOFTRST_CON25(Offset:0xA64)
543 #define SRST_ARESETN_VPU_BIU 0x00000196
544 #define SRST_HRESETN_VPU_BIU 0x00000197
545 #define SRST_PRESETN_VPU_BIU 0x00000198
546 #define SRST_ARESETN_VPU 0x00000199
547 #define SRST_HRESETN_VPU 0x0000019A
548 #define SRST_PRESETN_CRU_PCIE 0x0000019B
549 #define SRST_PRESETN_VPU_GRF 0x0000019C
550 #define SRST_HRESETN_SFC 0x0000019D
551 #define SRST_SRESETN_SFC 0x0000019E
552 #define SRST_CRESETN_EMMC 0x0000019F
554 // CRU_SOFTRST_CON26(Offset:0xA68)
555 #define SRST_HRESETN_EMMC 0x000001A0
556 #define SRST_ARESETN_EMMC 0x000001A1
557 #define SRST_BRESETN_EMMC 0x000001A2
558 #define SRST_TRESETN_EMMC 0x000001A3
559 #define SRST_PRESETN_GPIO1 0x000001A4
560 #define SRST_DBRESETN_GPIO1 0x000001A5
561 #define SRST_ARESETN_VPU_L_BIU 0x000001A6
562 #define SRST_PRESETN_VPU_IOC 0x000001A8
563 #define SRST_HRESETN_SAI_I2S0 0x000001A9
564 #define SRST_MRESETN_SAI_I2S0 0x000001AA
565 #define SRST_HRESETN_SAI_I2S2 0x000001AB
566 #define SRST_MRESETN_SAI_I2S2 0x000001AC
567 #define SRST_PRESETN_ACODEC 0x000001AD
569 // CRU_SOFTRST_CON27(Offset:0xA6C)
570 #define SRST_PRESETN_GPIO3 0x000001B0
571 #define SRST_DBRESETN_GPIO3 0x000001B1
572 #define SRST_PRESETN_SPI1 0x000001B4
573 #define SRST_RESETN_SPI1 0x000001B5
574 #define SRST_PRESETN_UART2 0x000001B7
575 #define SRST_SRESETN_UART2 0x000001B8
576 #define SRST_PRESETN_UART5 0x000001B9
577 #define SRST_SRESETN_UART5 0x000001BA
578 #define SRST_PRESETN_UART6 0x000001BB
579 #define SRST_SRESETN_UART6 0x000001BC
580 #define SRST_PRESETN_UART7 0x000001BD
581 #define SRST_SRESETN_UART7 0x000001BE
582 #define SRST_PRESETN_I2C3 0x000001BF
584 // CRU_SOFTRST_CON28(Offset:0xA70)
585 #define SRST_RESETN_I2C3 0x000001C0
586 #define SRST_PRESETN_I2C5 0x000001C1
587 #define SRST_RESETN_I2C5 0x000001C2
588 #define SRST_PRESETN_I2C6 0x000001C3
589 #define SRST_RESETN_I2C6 0x000001C4
590 #define SRST_ARESETN_MAC 0x000001C5
592 // CRU_SOFTRST_CON30(Offset:0xA78)
593 #define SRST_PRESETN_PCIE 0x000001E1
594 #define SRST_RESETN_PCIE_PIPE_PHY 0x000001E2
595 #define SRST_RESETN_PCIE_POWER_UP 0x000001E3
596 #define SRST_PRESETN_PCIE_PHY 0x000001E6
597 #define SRST_PRESETN_PIPE_GRF 0x000001E7
599 // CRU_SOFTRST_CON32(Offset:0xA80)
600 #define SRST_HRESETN_SDIO0 0x00000202
601 #define SRST_HRESETN_SDIO1 0x00000204
602 #define SRST_RESETN_TS_0 0x00000205
603 #define SRST_RESETN_TS_1 0x00000206
604 #define SRST_PRESETN_CAN2 0x00000207
605 #define SRST_RESETN_CAN2 0x00000208
606 #define SRST_PRESETN_CAN3 0x00000209
607 #define SRST_RESETN_CAN3 0x0000020A
608 #define SRST_PRESETN_SARADC 0x0000020B
609 #define SRST_RESETN_SARADC 0x0000020C
610 #define SRST_RESETN_SARADC_PHY 0x0000020D
611 #define SRST_PRESETN_TSADC 0x0000020E
612 #define SRST_RESETN_TSADC 0x0000020F
614 // CRU_SOFTRST_CON33(Offset:0xA84)
615 #define SRST_ARESETN_USB3OTG 0x00000211
617 // CRU_SOFTRST_CON34(Offset:0xA88)
618 #define SRST_ARESETN_GPU_BIU 0x00000223
619 #define SRST_PRESETN_GPU_BIU 0x00000225
620 #define SRST_ARESETN_GPU 0x00000228
621 #define SRST_RESETN_REF_PVTPLL_GPU 0x00000229
623 // CRU_SOFTRST_CON36(Offset:0xA90)
624 #define SRST_HRESETN_RKVENC_BIU 0x00000243
625 #define SRST_ARESETN_RKVENC_BIU 0x00000244
626 #define SRST_PRESETN_RKVENC_BIU 0x00000245
627 #define SRST_HRESETN_RKVENC 0x00000246
628 #define SRST_ARESETN_RKVENC 0x00000247
629 #define SRST_RESETN_CORE_RKVENC 0x00000248
630 #define SRST_HRESETN_SAI_I2S1 0x00000249
631 #define SRST_MRESETN_SAI_I2S1 0x0000024A
632 #define SRST_PRESETN_I2C1 0x0000024B
633 #define SRST_RESETN_I2C1 0x0000024C
634 #define SRST_PRESETN_I2C0 0x0000024D
635 #define SRST_RESETN_I2C0 0x0000024E
637 // CRU_SOFTRST_CON37(Offset:0xA94)
638 #define SRST_PRESETN_SPI0 0x00000252
639 #define SRST_RESETN_SPI0 0x00000253
640 #define SRST_PRESETN_GPIO4 0x00000258
641 #define SRST_DBRESETN_GPIO4 0x00000259
642 #define SRST_PRESETN_RKVENC_IOC 0x0000025A
643 #define SRST_HRESETN_SPDIF 0x0000025E
644 #define SRST_MRESETN_SPDIF 0x0000025F
646 // CRU_SOFTRST_CON38(Offset:0xA98)
647 #define SRST_HRESETN_PDM 0x00000260
648 #define SRST_MRESETN_PDM 0x00000261
649 #define SRST_PRESETN_UART1 0x00000262
650 #define SRST_SRESETN_UART1 0x00000263
651 #define SRST_PRESETN_UART3 0x00000264
652 #define SRST_SRESETN_UART3 0x00000265
653 #define SRST_PRESETN_RKVENC_GRF 0x00000266
654 #define SRST_PRESETN_CAN0 0x00000267
655 #define SRST_RESETN_CAN0 0x00000268
656 #define SRST_PRESETN_CAN1 0x00000269
657 #define SRST_RESETN_CAN1 0x0000026A
659 // CRU_SOFTRST_CON39(Offset:0xA9C)
660 #define SRST_ARESETN_VO_BIU 0x00000273
661 #define SRST_HRESETN_VO_BIU 0x00000274
662 #define SRST_PRESETN_VO_BIU 0x00000275
663 #define SRST_HRESETN_RGA2E 0x00000277
664 #define SRST_ARESETN_RGA2E 0x00000278
665 #define SRST_RESETN_CORE_RGA2E 0x00000279
666 #define SRST_HRESETN_VDPP 0x0000027A
667 #define SRST_ARESETN_VDPP 0x0000027B
668 #define SRST_RESETN_CORE_VDPP 0x0000027C
669 #define SRST_PRESETN_VO_GRF 0x0000027D
670 #define SRST_PRESETN_CRU 0x0000027F
672 // CRU_SOFTRST_CON40(Offset:0xAA0)
673 #define SRST_ARESETN_VOP_BIU 0x00000281
674 #define SRST_HRESETN_VOP 0x00000282
675 #define SRST_DRESETN_VOP0 0x00000283
676 #define SRST_DRESETN_VOP1 0x00000284
677 #define SRST_ARESETN_VOP 0x00000285
678 #define SRST_PRESETN_HDMI 0x00000286
679 #define SRST_HDMI_RESETN 0x00000287
680 #define SRST_PRESETN_HDMIPHY 0x0000028E
681 #define SRST_HRESETN_HDCP_KEY 0x0000028F
683 // CRU_SOFTRST_CON41(Offset:0xAA4)
684 #define SRST_ARESETN_HDCP 0x00000290
685 #define SRST_HRESETN_HDCP 0x00000291
686 #define SRST_PRESETN_HDCP 0x00000292
687 #define SRST_HRESETN_CVBS 0x00000293
688 #define SRST_DRESETN_CVBS_VOP 0x00000294
689 #define SRST_DRESETN_4X_CVBS_VOP 0x00000295
690 #define SRST_ARESETN_JPEG_DECODER 0x00000296
691 #define SRST_HRESETN_JPEG_DECODER 0x00000297
692 #define SRST_ARESETN_VO_L_BIU 0x00000299
693 #define SRST_ARESETN_MAC_VO 0x0000029A
695 // CRU_SOFTRST_CON42(Offset:0xAA8)
696 #define SRST_ARESETN_JPEG_BIU 0x000002A0
697 #define SRST_HRESETN_SAI_I2S3 0x000002A1
698 #define SRST_MRESETN_SAI_I2S3 0x000002A2
699 #define SRST_RESETN_MACPHY 0x000002A3
700 #define SRST_PRESETN_VCDCPHY 0x000002A4
701 #define SRST_PRESETN_GPIO2 0x000002A5
702 #define SRST_DBRESETN_GPIO2 0x000002A6
703 #define SRST_PRESETN_VO_IOC 0x000002A7
704 #define SRST_HRESETN_SDMMC0 0x000002A9
705 #define SRST_PRESETN_OTPC_NS 0x000002AB
706 #define SRST_RESETN_SBPI_OTPC_NS 0x000002AC
707 #define SRST_RESETN_USER_OTPC_NS 0x000002AD
709 // CRU_SOFTRST_CON43(Offset:0xAAC)
710 #define SRST_RESETN_HDMIHDP0 0x000002B2
711 #define SRST_HRESETN_USBHOST 0x000002B3
712 #define SRST_HRESETN_USBHOST_ARB 0x000002B4
713 #define SRST_RESETN_HOST_UTMI 0x000002B6
714 #define SRST_PRESETN_UART4 0x000002B7
715 #define SRST_SRESETN_UART4 0x000002B8
716 #define SRST_PRESETN_I2C4 0x000002B9
717 #define SRST_RESETN_I2C4 0x000002BA
718 #define SRST_PRESETN_I2C7 0x000002BB
719 #define SRST_RESETN_I2C7 0x000002BC
720 #define SRST_PRESETN_USBPHY 0x000002BD
721 #define SRST_RESETN_USBPHY_POR 0x000002BE
722 #define SRST_RESETN_USBPHY_OTG 0x000002BF
724 // CRU_SOFTRST_CON44(Offset:0xAB0)
725 #define SRST_RESETN_USBPHY_HOST 0x000002C0
726 #define SRST_PRESETN_DDRPHY_CRU 0x000002C4
727 #define SRST_HRESETN_RKVDEC_BIU 0x000002C6
728 #define SRST_ARESETN_RKVDEC_BIU 0x000002C7
729 #define SRST_ARESETN_RKVDEC 0x000002C8
730 #define SRST_HRESETN_RKVDEC 0x000002C9
731 #define SRST_RESETN_HEVC_CA_RKVDEC 0x000002CB
732 #define SRST_RESETN_REF_PVTPLL_RKVDEC 0x000002CC
734 // CRU_SOFTRST_CON45(Offset:0xAB4)
735 #define SRST_PRESETN_DDR_BIU 0x000002D1
736 #define SRST_PRESETN_DDRC 0x000002D2
737 #define SRST_PRESETN_DDRMON 0x000002D3
738 #define SRST_RESETN_TIMER_DDRMON 0x000002D4
739 #define SRST_PRESETN_MSCH_BIU 0x000002D5
740 #define SRST_PRESETN_DDR_GRF 0x000002D6
741 #define SRST_PRESETN_DDR_HWLP 0x000002D8
742 #define SRST_PRESETN_DDRPHY 0x000002D9
743 #define SRST_RESETN_MSCH_BIU 0x000002DA
744 #define SRST_ARESETN_DDR_UPCTL 0x000002DB
745 #define SRST_RESETN_DDR_UPCTL 0x000002DC
746 #define SRST_RESETN_DDRMON 0x000002DD
747 #define SRST_ARESETN_DDR_SCRAMBLE 0x000002DE
748 #define SRST_ARESETN_SPLIT 0x000002DF
750 // CRU_SOFTRST_CON46(Offset:0xAB8)
751 #define SRST_RESETN_DDR_PHY 0x000002E0