1019 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1020 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1117 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_max_link_rate()
1119 	return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);  in drm_dp_max_link_rate()
1123 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_max_lane_count()
1125 	return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;  in drm_dp_max_lane_count()
1129 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_enhanced_frame_cap()
1131 	return dpcd[DP_DPCD_REV] >= 0x11 &&  in drm_dp_enhanced_frame_cap()
1132 		(dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);  in drm_dp_enhanced_frame_cap()
1136 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_tps3_supported()
1138 	return dpcd[DP_DPCD_REV] >= 0x12 &&  in drm_dp_tps3_supported()
1139 		dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;  in drm_dp_tps3_supported()
1143 drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_tps4_supported()
1145 	return dpcd[DP_DPCD_REV] >= 0x14 &&  in drm_dp_tps4_supported()
1146 		dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED;  in drm_dp_tps4_supported()
1150 drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_training_pattern_mask()
1152 	return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :  in drm_dp_training_pattern_mask()
1157 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_is_branch()
1159 	return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;  in drm_dp_is_branch()
1163 drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_channel_coding_supported()
1165 	return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B;  in drm_dp_channel_coding_supported()
1222 			  u8 dpcd[DP_RECEIVER_CAP_SIZE]);