u-boot/include/ddr_spd.h

2  * Copyright 2008-2014 Freescale Semiconductor, Inc.
4  * SPDX-License-Identifier:	GPL-2.0
11  * Format from "JEDEC Standard No. 21-C,
21 	unsigned char dataw_lsb;   /*  6 Data Width of this assembly */
22 	unsigned char dataw_msb;   /*  7 ... Data Width continuation */
38 	unsigned char clk_cycle2;  /* 23 Min SDRAM Cycle time @ CL=X-0.5 */
40 					 Clk @ CL=X-0.5 (tAC) */
41 	unsigned char clk_cycle3;  /* 25 Min SDRAM Cycle time @ CL=X-1 */
42 	unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-1 (tAC) */
44 	unsigned char trrd;        /* 28 Min Row Active to Row Active (tRRD) */
50 	unsigned char data_setup;  /* 34 Data Input Setup Time Before Strobe */
51 	unsigned char data_hold;   /* 35 Data Input Hold Time After Strobe */
52 	unsigned char res_36_40[5];/* 36-40 reserved for VCSDRAM */
53 	unsigned char trc;         /* 41 Min Active to Auto refresh time tRC */
54 	unsigned char trfc;        /* 42 Min Auto to Active period tRFC */
60 	unsigned char res_48_61[14]; /* 48-61 Reserved */
61 	unsigned char spd_rev;     /* 62 SPD Data Revision Code */
62 	unsigned char cksum;       /* 63 Checksum for bytes 0-62 */
63 	unsigned char mid[8];      /* 64-71 Mfr's JEDEC ID code per JEP-106 */
69 	unsigned char mspec[27];   /* 99-127 Manufacturer Specific Data */
84 	unsigned char dataw;       /*  6 Module Data Width */
101 	unsigned char clk_cycle2;  /* 23 Min SDRAM Cycle time @ CL=X-1 */
102 	unsigned char clk_access2; /* 24 SDRAM Access from Clk @ CL=X-1 (tAC) */
103 	unsigned char clk_cycle3;  /* 25 Min SDRAM Cycle time @ CL=X-2 */
104 	unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-2 (tAC) */
106 	unsigned char trrd;        /* 28 Min Row Active to Row Active (tRRD) */
112 	unsigned char data_setup;  /* 34 Data Input Setup Time
114 	unsigned char data_hold;   /* 35 Data Input Hold Time
121 	unsigned char trc;         /* 41 Min Active to Auto refresh time tRC */
122 	unsigned char trfc;        /* 42 Min Auto to Active period tRFC */
129 					 Top (Case) to Ambient (Psi T-A DRAM) */
131 					 due to Activate-Precharge/Mode Bits
137 					 due to Precharge Power-Down (DT2P) */
139 					 due to Active Standby (DT3N) */
141 					 due to Active Power-Down with
144 					 due to Active Power-Down with Slow
153 					 Auto-Precharge (DT7) */
155 					 Top (Case) to Ambient (Psi T-A PLL) */
158 					 (Psi T-A Register) */
160 					 due to PLL Active (DT PLL Active) */
162 					 Ambient due to Register Active/Mode Bit
163 					 (DT Register Active/Mode Bit) */
164 	unsigned char spd_rev;     /* 62 SPD Data Revision Code */
165 	unsigned char cksum;       /* 63 Checksum for bytes 0-62 */
166 	unsigned char mid[8];      /* 64 Mfr's JEDEC ID code per JEP-106 */
172 	unsigned char mspec[27];   /* 99-127 Manufacturer Specific Data */
177 	/* General Section: Bytes 0-59 */
201 	unsigned char trrd_min;        /* 19 Min Row Active to
202 					     Row Active Delay Time */
205 	unsigned char tras_min_lsb;    /* 22 Min Active to Precharge
207 	unsigned char trc_min_lsb;     /* 23 Min Active to Active/Refresh
227 	unsigned char res_39_59[21];   /* 39-59 Reserved, General Section */
229 	/* Module-Specific Section: Bytes 60-116 */
241 			/* 64-116 (Unbuffered) Reserved */
263 			/* 69-76 RC1,3,5...15 (MS Nibble) / RC0,2,4...14 (LS Nibble) */
266 		unsigned char uc[57]; /* 60-116 Module-Specific Section */
269 	/* Unique Module ID: Bytes 117-125 */
270 	unsigned char mmid_lsb;        /* 117 Module MfgID Code LSB - JEP-106 */
271 	unsigned char mmid_msb;        /* 118 Module MfgID Code MSB - JEP-106 */
273 	unsigned char mdate[2];        /* 120-121 Mfg Date */
274 	unsigned char sernum[4];       /* 122-125 Module Serial Number */
276 	/* CRC: Bytes 126-127 */
277 	unsigned char crc[2];          /* 126-127 SPD CRC */
279 	/* Other Manufacturer Fields and User Space: Bytes 128-255 */
280 	unsigned char mpart[18];       /* 128-145 Mfg's Module Part Number */
281 	unsigned char mrev[2];         /* 146-147 Module Revision Code */
283 	unsigned char dmid_lsb;        /* 148 DRAM MfgID Code LSB - JEP-106 */
284 	unsigned char dmid_msb;        /* 149 DRAM MfgID Code MSB - JEP-106 */
286 	unsigned char msd[26];         /* 150-175 Mfg's Specific Data */
287 	unsigned char cust[80];        /* 176-255 Open for Customer Use */
291 /* From JEEC Standard No. 21-C release 23A */
293 	/* General Section: Bytes 0-127 */
335 	uint8_t res_41[60-41];		/* 41 Rserved */
336 	uint8_t mapping[78-60];		/* 60~77 Connector to SDRAM bit map */
337 	uint8_t res_78[117-78];		/* 78~116, Reserved */
347 	/* CRC: Bytes 126-127 */
348 	uint8_t crc[2];			/* 126-127 SPD CRC */
350 	/* Module-Specific Section: Bytes 128-255 */
363 			uint8_t res_132[254-132];
387 			uint8_t res_137[254-137];
414 			/* 139 Data Buffer Revision Number */
424 			/* 144 Data Buffer VrefDQ for DRAM Interface */
427 			 * 145 Data Buffer MDQ Drive Strength and RTT
428 			 * for data rate <= 1866
432 			 * 146 Data Buffer MDQ Drive Strength and RTT
433 			 * for 1866 < data rate <= 2400
437 			 * 147 Data Buffer MDQ Drive Strength and RTT
438 			 * for 2400 < data rate <= 3200
445 			 * for data rate <= 1866
450 			 * for 1866 < data rate <= 2400
455 			 * for 2400 < data rate <= 3200
460 			 * for data rate <= 1866
465 			 * for 1866 < data rate <= 2400
470 			 * for 2400 < data rate <= 3200
473 			uint8_t res_155[254-155];	/* Reserved */
477 		uint8_t uc[128]; /* 128-255 Module-Specific Section */
480 	uint8_t res_256[320-256];	/* 256~319 Reserved */
482 	/* Module supplier's data: Byte 320~383 */
493 	uint8_t msd[29];		/* 353~381 Mfg's Specific Data */
496 	uint8_t user[512-384];		/* 384~511 End User Programmable */