Lines Matching +full:0 +full:xfff00000
20 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
26 #define CONFIG_SYS_TEXT_BASE 0xfff00000
40 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
41 #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
42 #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
43 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
48 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
51 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
57 #define CONFIG_SYS_SCRATCH_VA 0xe0000000
63 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */
69 #define L2_INIT 0
76 #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
79 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
86 #define CONFIG_SYS_MEMTEST_START 0x10000000
87 #define CONFIG_SYS_MEMTEST_END 0x20000000
90 /* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
91 #define I2C_ADDR_IGNORE_LIST {0x50}
95 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
96 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
97 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
98 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
99 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
100 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
101 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
102 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
103 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
104 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
112 #define CONFIG_SYS_NAND_BASE 0xef800000
113 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
119 #define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */
126 #define CONFIG_SYS_FLASH_BASE 0xf8000000
127 #define CONFIG_SYS_FLASH_BASE2 0xf0000000
136 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \
137 {0xf7f00000, 0xc0000} }
139 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
144 /* NOR Flash 0 on CS0 */
185 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
186 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
200 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
201 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
202 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
214 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
215 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
217 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
218 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
221 #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
224 #define CONFIG_SYS_I2C_LM90_ADDR 0x4c
227 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
234 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
239 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
240 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
241 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
242 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
244 #define CONFIG_SYS_I2C_PCA9553_ADDR 0x62
250 /* PCA9557 @ 0x18*/
251 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
252 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
253 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
254 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
255 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
256 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
258 /* PCA9557 @ 0x1c*/
259 #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
260 #define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */
261 #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
262 #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
263 #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
264 #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
265 #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
266 #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
268 /* PCA9557 @ 0x1e*/
269 #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
270 #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
271 #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
272 #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
273 #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
274 #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */
275 #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */
277 /* PCA9557 @ 0x1f */
278 #define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */
279 #define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */
280 #define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */
281 #define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */
285 * Memory space is mapped 1-1, but I/O space must start from 0.
288 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
290 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
291 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
292 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
293 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
296 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
298 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
299 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
300 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
301 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
314 #define TSEC1_PHYIDX 0
321 #define TSEC2_PHYIDX 0
344 * 0x0000_0000 2G DDR
353 * 0x8000_0000 1G PCI-Express 1 Memory
370 * 0xc000_0000 512M PCI-Express 2 Memory
387 * 0xe000_0000 1M CCSR
404 * 0xe200_0000 16M PCI-Express 1 I/O
405 * 0xe300_0000 16M PCI-Express 2 I/0
422 * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory)
436 * 0xf000_0000 256M FLASH
467 * 0xe800_0000 64K NAND FLASH
468 * 0xe804_0000 128K DUART Registers
487 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
489 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
504 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
505 #define CONFIG_ENV_SIZE 0x8000
522 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff00000)
523 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f00000)
524 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfffc0000)
525 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7fc0000)
526 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
527 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
531 "if test $? -eq 0; then " \
537 "if test $? -ne 0; then " \
548 "if test $? -eq 0; then " \
554 "if test $? -ne 0; then " \
565 "if test $? -eq 0; then " \
568 "if test $? -eq 0; then " \
582 "if test $? -eq 0; then " \
586 "if test $? -ne 0; then " \
597 "if test $? -eq 0; then " \
601 "if test $? -ne 0; then " \
612 "if test $? -eq 0; then " \
616 "if test $? -ne 0; then " \
627 "if test $? -eq 0; then " \
631 "if test $? -ne 0; then " \
641 "autoload=yes\0" \
642 "download_cmd=tftp\0" \
643 "console_args=console=ttyS0,115200\0" \
644 "root_args=root=/dev/nfs rw\0" \
645 "misc_args=ip=on\0" \
646 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
647 "bootfile=/home/user/file\0" \
648 "osfile=/home/user/board.uImage\0" \
649 "fdtfile=/home/user/board.dtb\0" \
650 "ubootfile=/home/user/u-boot.bin\0" \
651 "fdtaddr=0x1e00000\0" \
652 "osaddr=0x1000000\0" \
653 "loadaddr=0x1000000\0" \
654 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
655 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
656 "prog_os1="CONFIG_PROG_OS1"\0" \
657 "prog_os2="CONFIG_PROG_OS2"\0" \
658 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
659 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
660 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
662 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
664 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
665 "bootcmd=run bootcmd_flash1\0"