Lines Matching +full:0 +full:xfe000000
25 #define CONFIG_SYS_TEXT_BASE 0xfe000000
39 #define CONFIG_SYS_IMMR 0xE0000000
41 #define CONFIG_SYS_MEMTEST_START 0x00001000
42 #define CONFIG_SYS_MEMTEST_END 0x07000000
54 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
69 /* 0x80840102 */
71 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
72 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
73 | (0 << TIMING_CFG0_WRT_SHIFT) \
80 /* 0x0e720802 */
89 /* 0x26256222 */
90 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
97 /* 0x029028c7 */
98 #define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \
99 | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
100 /* 0x03202000 */
104 /* 0x43080000 */
105 #define CONFIG_SYS_SDRAM_CFG2 0x00401000
106 #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
107 | (0x0232 << SDRAM_MODE_SD_SHIFT))
108 /* 0x44400232 */
109 #define CONFIG_SYS_DDR_MODE_2 0x8000C000
112 /*0x02000000*/
117 /* 0x73000002 */
124 #define CONFIG_SYS_FLASH_BASE 0xFE000000
139 /* 0xfe000c55 */
157 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
158 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
174 #define CONFIG_SYS_LBC_LBCR 0x00040000
176 #define CONFIG_SYS_LBC_MRTPR 0x20000000
181 #define CONFIG_SYS_NAND_BASE 0x61000000
191 /* 0x61000c21 */
198 /* 0xffff90ac */
212 #define CONFIG_SYS_BR2_PRELIM (0x60000000 \
215 /* 0x60000801 */
223 /* 0xfffe0937 */
224 /* local bus read write buffer mapping SRAM@0x64000000 */
225 #define CONFIG_SYS_BR3_PRELIM (0x62000000 \
228 /* 0x62001001 */
237 /* 0xfe0009f7 */
245 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
250 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
251 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
258 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
260 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
261 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
263 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
264 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
265 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
266 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
268 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
280 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
281 #define TSEC1_PHY_ADDR 0x01
282 #define TSEC1_FLAGS 0
283 #define TSEC1_PHYIDX 0
286 /* Options are: TSEC[0-1] */
294 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
295 #define CONFIG_ENV_SIZE 0x4000
323 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
336 /* 0x64050000 */
338 0x20000000 /* reserved, must be set */ |\
343 /* 0xa0600004 */
356 #define CONFIG_SYS_SICRH (0x01000000 | \
365 /* 0x010fff03 */
372 /* 0x33fc0003) */
374 #define CONFIG_SYS_HID0_INIT 0x000000000
382 /* DDR @ 0x00000000 */
390 /* PCI @ 0x80000000 */
405 #define CONFIG_SYS_IBAT1L (0)
406 #define CONFIG_SYS_IBAT1U (0)
407 #define CONFIG_SYS_IBAT2L (0)
408 #define CONFIG_SYS_IBAT2U (0)
412 #define CONFIG_SYS_IBAT3L (0)
413 #define CONFIG_SYS_IBAT3U (0)
414 #define CONFIG_SYS_IBAT4L (0)
415 #define CONFIG_SYS_IBAT4U (0)
417 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
427 /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
428 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
429 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
431 /* FPGA, SRAM, NAND @ 0x60000000 */
432 #define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
433 #define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP)
458 "netdev=" __stringify(CONFIG_NETDEV) "\0" \
459 "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0" \
460 "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0" \
461 "u-boot_addr_r=100000\0" \
462 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
468 "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \