include/configs/t4qds.h

18 #define CONFIG_SYS_TEXT_BASE	0xeff40000
22 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
46 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
54 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
55 #define CONFIG_SYS_MEMTEST_END		0x00400000
61 #define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
72 #define CONFIG_SYS_DCSRBAR		0xf0000000
73 #define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
79 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
91 #define CONFIG_SYS_FLASH_BASE	0xe0000000
92 #define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
108 #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
109 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
110 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
115 #define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
131 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
136 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
137 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
138 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
139 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
144 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
145 #define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
146 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
147 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
152 #define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
153 #define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
154 #define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */
156 #define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
157 #define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
158 #define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
162  * Memory space is mapped 1-1, but I/O space must start from 0.
166 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
167 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
168 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
169 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
170 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
171 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
172 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
173 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
176 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
177 #define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
178 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
179 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
180 #define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
181 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
182 #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
183 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
186 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
187 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
188 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
189 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
190 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
191 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
192 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
193 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
196 #define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
197 #define CONFIG_SYS_PCIE4_MEM_PHYS	0xc60000000ull
198 #define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
199 #define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
200 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
201 #define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
246 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
271  "setenv bootargs config-addr=0x60000000; "	\
272  "bootm 0x01000000 - 0x00f00000"