Lines Matching +full:0 +full:xe2800000
49 #define CONFIG_SYS_TEXT_BASE 0xfff00000
51 #define CONFIG_SYS_TEXT_BASE 0xfffa0000
90 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
91 #define CONFIG_SYS_MEMTEST_END 0x00400000
93 #define CONFIG_SYS_CCSRBAR 0xe0000000
105 * for a device at 0x53.
111 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
113 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
122 * SPD at 0x53, but if we are running on an older board w/o the
123 * fix, it will still be at 0x51. We check 0x53 1st.
125 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
126 #define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */
133 #define CONFIG_SYS_DDR_CONTROL 0xc300c000
153 * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
159 * Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0
162 * 0 4 8 12 16 20 24 28
166 #define CONFIG_SYS_BR0_8M 0xff800801
167 #define CONFIG_SYS_BR0_64M 0xfc001801
171 * Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0
177 * Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0
180 * 0 4 8 12 16 20 24 28
184 #define CONFIG_SYS_BR6_8M 0xef800801
185 #define CONFIG_SYS_BR6_64M 0xec001801
189 * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
198 * Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0
201 * 0 4 8 12 16 20 24 28
205 #define CONFIG_SYS_OR0_8M 0xff806e65
206 #define CONFIG_SYS_OR0_64M 0xfc006e65
210 * Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0
219 * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
221 * 0 4 8 12 16 20 24 28
225 #define CONFIG_SYS_OR6_8M 0xff806e65
226 #define CONFIG_SYS_OR6_64M 0xfc006e65
229 #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */
230 #define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */
238 #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* start 64MB Flash */
239 #define CONFIG_SYS_ALT_FLASH 0xef800000 /* 8MB soldered flash */
265 #define CONFIG_SYS_BR5_PRELIM 0xf8000801
266 #define CONFIG_SYS_OR5_PRELIM 0xff006e65
267 #define CONFIG_SYS_EPLD_BASE 0xf8000000
268 #define CONFIG_SYS_LED_DISP_BASE 0xf8000000
269 #define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000
270 #define CONFIG_SYS_BD_REV 0xf8300000
271 #define CONFIG_SYS_EEPROM_BASE 0xf8b00000
276 * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible
280 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
285 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
288 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
294 * 0 4 8 12 16 20 24 28
299 #define CONFIG_SYS_BR3_PRELIM 0xf0001861
305 * 64MB mask for AM, OR3[0:7] = 1111 1100
309 * EAD set for extra time OR[31] = 0
311 * 0 4 8 12 16 20 24 28
315 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0
319 * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000.
322 * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0
328 * 0 4 8 12 16 20 24 28
333 #define CONFIG_SYS_BR4_PRELIM 0xf4001861
339 * 64MB mask for AM, OR3[0:7] = 1111 1100
343 * EAD set for extra time OR[31] = 0
345 * 0 4 8 12 16 20 24 28
349 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0
351 #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */
352 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
353 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
354 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
379 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
380 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
382 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
389 * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM
391 * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right
406 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
407 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
415 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
416 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
417 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
421 * Memory space is mapped 1-1, but I/O space must start from 0.
423 #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */
424 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
426 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
427 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
428 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
429 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
430 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
431 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
432 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
433 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
436 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
437 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
438 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
439 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
440 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
441 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
442 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
443 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
450 #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000
451 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
471 #define TSEC1_PHY_ADDR 0x19
472 #define TSEC2_PHY_ADDR 0x1a
474 #define TSEC1_PHYIDX 0
475 #define TSEC2_PHYIDX 0
480 /* Options are: eTSEC[0-3] */
487 #define CONFIG_ENV_SIZE 0x2000
488 #if CONFIG_SYS_TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */
489 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000)
490 #define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */
491 #elif CONFIG_SYS_TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */
492 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
493 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
517 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
552 "netdev=eth0\0" \
553 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
559 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
560 "consoledev=ttyS0\0" \
561 "ramdiskaddr=2000000\0" \
562 "ramdiskfile=uRamdisk\0" \
563 "fdtaddr=1e00000\0" \
564 "fdtfile=sbc8548.dtb\0"