Lines Matching +full:0 +full:x80010000

31 #define CONFIG_SPL_TEXT_BASE	0x87dc0000
32 #define CONFIG_SYS_TEXT_BASE	0x87e00000
72 	"bootargs_base=setenv bootargs console=ttymxc0,115200\0"	\
74 		"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"	\
75 	"bootcmd=run bootcmd_net\0"					\
77 		"tftpboot 0x81000000 uImage-mx31; bootm\0"		\
78 	"prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; "		\
79 		"nand erase 0x0 0x40000; "				\
80 		"nand write 0x81000000 0x0 0x40000\0"
83 #define CONFIG_SMC911X_BASE	0xB6000000
92 #define CONFIG_SYS_MEMTEST_START	0x80000000
93 #define CONFIG_SYS_MEMTEST_END		0x80010000
96 #define CONFIG_SYS_LOAD_ADDR		0x81000000
118 #define CONFIG_ENV_OFFSET		0x40000
119 #define CONFIG_ENV_OFFSET_REDUND	0x60000
135 #define CONFIG_SYS_NAND_U_BOOT_SIZE	0x3f800
140 #define CONFIG_SYS_NAND_PAGE_SIZE	0x800
144 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
147 #define CCM_CCMR_SETUP		0x074B0BF5
148 #define CCM_PDR0_SETUP_532MHZ	(PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
151 				 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
152 #define CCM_MPCTL_SETUP_532MHZ	(PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) |  \
155 #define ESDMISC_MDDR_SETUP	0x00000004
156 #define ESDMISC_MDDR_RESET_DL	0x0000000c
157 #define ESDCFG0_MDDR_SETUP	0x006ac73a