Lines Matching +full:0 +full:x65000000
24 #define I2C_MUX_CH_VOL_MONITOR 0xa
25 #define I2C_VOL_MONITOR_ADDR 0x38
51 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
52 #define SPD_EEPROM_ADDRESS1 0x51
53 #define SPD_EEPROM_ADDRESS2 0x52
54 #define SPD_EEPROM_ADDRESS3 0x53
55 #define SPD_EEPROM_ADDRESS4 0x54
56 #define SPD_EEPROM_ADDRESS5 0x55
57 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
59 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
83 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
98 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
99 FTIM0_NOR_TEADC(0x5) | \
100 FTIM0_NOR_TEAHC(0x5))
101 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
102 FTIM1_NOR_TRAD_NOR(0x1a) |\
103 FTIM1_NOR_TSEQRAD_NOR(0x13))
104 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
105 FTIM2_NOR_TCH(0x4) | \
106 FTIM2_NOR_TWPH(0x0E) | \
107 FTIM2_NOR_TWP(0x1c))
108 #define CONFIG_SYS_NOR_FTIM3 0x04000000
109 #define CONFIG_SYS_IFC_CCR 0x01000000
125 CONFIG_SYS_FLASH_BASE + 0x40000000}
132 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
150 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
151 FTIM0_NAND_TWP(0x30) | \
152 FTIM0_NAND_TWCHT(0x0e) | \
153 FTIM0_NAND_TWH(0x14))
154 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
155 FTIM1_NAND_TWBE(0xab) | \
156 FTIM1_NAND_TRR(0x1c) | \
157 FTIM1_NAND_TRP(0x30))
158 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
159 FTIM2_NAND_TREH(0x14) | \
160 FTIM2_NAND_TWHRE(0x3c))
161 #define CONFIG_SYS_NAND_FTIM3 0x0
169 #define QIXIS_LBMAP_SWITCH 0x06
170 #define QIXIS_LBMAP_MASK 0x0f
171 #define QIXIS_LBMAP_SHIFT 0
172 #define QIXIS_LBMAP_DFLTBANK 0x00
173 #define QIXIS_LBMAP_ALTBANK 0x04
174 #define QIXIS_LBMAP_NAND 0x09
175 #define QIXIS_RST_CTL_RESET 0x31
176 #define QIXIS_RST_CTL_RESET_EN 0x30
177 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
178 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
179 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
180 #define QIXIS_RCW_SRC_NAND 0x119
181 #define QIXIS_RST_FORCE_MEM 0x01
183 #define CONFIG_SYS_CSPR3_EXT (0x0)
196 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
197 FTIM0_GPCM_TEADC(0x0e) | \
198 FTIM0_GPCM_TEAHC(0x0e))
199 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
200 FTIM1_GPCM_TRAD(0x3f))
201 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
202 FTIM2_GPCM_TCH(0xf) | \
203 FTIM2_GPCM_TWP(0x3E))
204 #define CONFIG_SYS_CS3_FTIM3 0x0
226 #define CONFIG_ENV_SECT_SIZE 0x20000
227 #define CONFIG_ENV_SIZE 0x2000
228 #define CONFIG_SPL_PAD_TO 0x80000
250 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
251 #define CONFIG_ENV_SECT_SIZE 0x20000
252 #define CONFIG_ENV_SIZE 0x2000
257 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
263 #define QIXIS_QMAP_MASK 0x07
265 #define QIXIS_LBMAP_DFLTBANK 0x00
266 #define QIXIS_LBMAP_QSPI 0x00
267 #define QIXIS_RCW_SRC_QSPI 0x62
268 #define QIXIS_LBMAP_ALTBANK 0x20
269 #define QIXIS_RST_CTL_RESET 0x31
270 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
271 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
272 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
273 #define QIXIS_LBMAP_MASK 0x0f
274 #define QIXIS_RST_CTL_RESET_EN 0x30
281 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
283 #define I2C_MUX_PCA_ADDR 0x75
284 #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
287 #define I2C_MUX_CH_DEFAULT 0x8
312 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
315 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
321 #define CONFIG_SYS_EEPROM_BUS_NUM 0
322 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
352 func(USB, usb, 0) \
353 func(MMC, mmc, 0) \
354 func(SCSI, scsi, 0) \
361 "esbc_validate 0x20700000 && " \
362 "esbc_validate 0x20740000;" \
363 "fsl_mc start mc 0x20a00000 0x20e00000 \0"
367 "esbc_validate 0x580700000 && " \
368 "esbc_validate 0x580740000; " \
369 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
375 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
376 "ramdisk_addr=0x800000\0" \
377 "ramdisk_size=0x2000000\0" \
378 "fdt_high=0xa0000000\0" \
379 "initrd_high=0xffffffffffffffff\0" \
380 "fdt_addr=0x64f00000\0" \
381 "kernel_addr=0x65000000\0" \
382 "kernel_start=0x1000000\0" \
383 "kernelheader_start=0x800000\0" \
384 "scriptaddr=0x80000000\0" \
385 "scripthdraddr=0x80080000\0" \
386 "fdtheader_addr_r=0x80100000\0" \
387 "kernelheader_addr_r=0x80200000\0" \
388 "kernelheader_addr=0x580800000\0" \
389 "kernel_addr_r=0x81000000\0" \
390 "kernelheader_size=0x40000\0" \
391 "fdt_addr_r=0x90000000\0" \
392 "load_addr=0xa0000000\0" \
393 "kernel_size=0x2800000\0" \
394 "console=ttyAMA0,38400n8\0" \
397 "boot_scripts=ls2088ardb_boot.scr\0" \
398 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
408 "done\0" \
414 "done;\0" \
422 "source ${scriptaddr}\0" \
423 "installer=load mmc 0:2 $load_addr " \
425 "bootm $load_addr#ls2088ardb\0" \
431 " bootm $load_addr#$board\0" \
437 "bootm $load_addr#$board\0"
444 "&& esbc_validate 0x20780000; " \
446 "fsl_mc lazyapply dpl 0x20d00000; " \
453 "&& esbc_validate 0x580780000; env exists mcinitcmd "\
454 "&& fsl_mc lazyapply dpl 0x580d00000;" \
466 #define CONFIG_CORTINA_FW_ADDR 0x20980000
468 #define CONFIG_CORTINA_FW_ADDR 0x580980000
470 #define CONFIG_CORTINA_FW_LENGTH 0x40000
472 #define CORTINA_PHY_ADDR1 0x10
473 #define CORTINA_PHY_ADDR2 0x11
474 #define CORTINA_PHY_ADDR3 0x12
475 #define CORTINA_PHY_ADDR4 0x13
476 #define AQ_PHY_ADDR1 0x00
477 #define AQ_PHY_ADDR2 0x01
478 #define AQ_PHY_ADDR3 0x02
479 #define AQ_PHY_ADDR4 0x03
480 #define AQR405_IRQ_MASK 0x36