Lines Matching +full:0 +full:x4100000
13 #define CONFIG_SYS_TEXT_BASE 0x82000000
15 #define CONFIG_SYS_TEXT_BASE 0x40100000
17 #define CONFIG_SYS_TEXT_BASE 0x60100000
38 #define SPD_EEPROM_ADDRESS 0x51
39 #define CONFIG_SYS_SPD_BUS_NUM 0
48 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
58 #define CONFIG_SF_DEFAULT_CS 0
76 #define RGMII_PHY1_ADDR 0x1
77 #define RGMII_PHY2_ADDR 0x2
78 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
79 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
80 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
81 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
83 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
84 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
85 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
86 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
116 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
118 #define CONFIG_SYS_FLASH_BASE 0x60000000
120 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
134 #define CFG_UART_MUX_MASK 0x6
136 #define CFG_LPUART_EN 0x2
154 #define CONFIG_SYS_EEPROM_BUS_NUM 0
155 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
171 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
176 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
178 + 0x8000000) | \
186 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
187 FTIM0_NOR_TEADC(0x5) | \
188 FTIM0_NOR_TEAHC(0x5))
189 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
190 FTIM1_NOR_TRAD_NOR(0x1a) | \
191 FTIM1_NOR_TSEQRAD_NOR(0x13))
192 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
193 FTIM2_NOR_TCH(0x4) | \
194 FTIM2_NOR_TWPH(0xe) | \
195 FTIM2_NOR_TWP(0x1c))
196 #define CONFIG_SYS_NOR_FTIM3 0
205 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
215 #define CONFIG_SYS_NAND_BASE 0x7e800000
218 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
235 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
236 FTIM0_NAND_TWP(0x18) | \
237 FTIM0_NAND_TWCHT(0x7) | \
238 FTIM0_NAND_TWH(0xa))
239 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
240 FTIM1_NAND_TWBE(0x39) | \
241 FTIM1_NAND_TRR(0xe) | \
242 FTIM1_NAND_TRP(0x18))
243 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
244 FTIM2_NAND_TREH(0xa) | \
245 FTIM2_NAND_TWHRE(0x1e))
246 #define CONFIG_SYS_NAND_FTIM3 0x0
256 #define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */
272 #define QIXIS_BASE 0x7fb00000
274 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
276 #define QIXIS_LBMAP_MASK 0x0f
277 #define QIXIS_LBMAP_SHIFT 0
278 #define QIXIS_LBMAP_DFLTBANK 0x00
279 #define QIXIS_LBMAP_ALTBANK 0x04
280 #define QIXIS_LBMAP_NAND 0x09
281 #define QIXIS_LBMAP_SD 0x00
282 #define QIXIS_LBMAP_SD_QSPI 0xff
283 #define QIXIS_LBMAP_QSPI 0xff
284 #define QIXIS_RCW_SRC_NAND 0x110
285 #define QIXIS_RCW_SRC_SD 0x040
286 #define QIXIS_RCW_SRC_QSPI 0x045
287 #define QIXIS_RST_CTL_RESET 0x41
288 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
289 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
290 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
292 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
305 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
306 FTIM0_GPCM_TEADC(0x20) | \
307 FTIM0_GPCM_TEAHC(0x10))
308 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
309 FTIM1_GPCM_TRAD(0x1f))
310 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
311 FTIM2_GPCM_TCH(0x8) | \
312 FTIM2_GPCM_TWP(0xf0))
313 #define CONFIG_SYS_FPGA_FTIM3 0x0
387 #define I2C_MUX_PCA_ADDR_PRI 0x77
388 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
389 #define I2C_RETIMER_ADDR 0x18
390 #define I2C_MUX_CH_DEFAULT 0x8
391 #define I2C_MUX_CH_CH7301 0xC
392 #define I2C_MUX_CH5 0xD
393 #define I2C_MUX_CH6 0xE
394 #define I2C_MUX_CH7 0xF
396 #define I2C_MUX_CH_VOL_MONITOR 0xa
399 #define I2C_VOL_MONITOR_ADDR 0x40
400 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
401 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
421 #define CONFIG_SYS_MEMTEST_START 0x80000000
422 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
437 #define CONFIG_ENV_SIZE 0x2000
441 #define CONFIG_SYS_MMC_ENV_DEV 0
442 #define CONFIG_ENV_SIZE 0x2000
444 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
445 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
446 #define CONFIG_ENV_SECT_SIZE 0x10000
448 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
449 #define CONFIG_ENV_SECT_SIZE 0x20000
450 #define CONFIG_ENV_SIZE 0x20000
469 "2m@0x100000(nor_bank0_uboot),"\
470 "40m@0x1100000(nor_bank0_fit)," \
472 "2m@0x4100000(nor_bank4_uboot)," \
473 "40m@0x5100000(nor_bank4_fit),"\
477 "472m(nand_free);spi0.0:2m(uboot)," \