Lines Matching +full:0 +full:x65000000
58 #define DDR_SDRAM_CFG 0x470c0008
59 #define DDR_CS0_BNDS 0x008000bf
60 #define DDR_CS0_CONFIG 0x80014302
61 #define DDR_TIMING_CFG_0 0x50550004
62 #define DDR_TIMING_CFG_1 0xbcb38c56
63 #define DDR_TIMING_CFG_2 0x0040d120
64 #define DDR_TIMING_CFG_3 0x010e1000
65 #define DDR_TIMING_CFG_4 0x00000001
66 #define DDR_TIMING_CFG_5 0x03401400
67 #define DDR_SDRAM_CFG_2 0x00401010
68 #define DDR_SDRAM_MODE 0x00061c60
69 #define DDR_SDRAM_MODE_2 0x00180000
70 #define DDR_SDRAM_INTERVAL 0x18600618
71 #define DDR_DDR_WRLVL_CNTL 0x8655f605
72 #define DDR_DDR_WRLVL_CNTL_2 0x05060607
73 #define DDR_DDR_WRLVL_CNTL_3 0x05050505
74 #define DDR_DDR_CDR1 0x80040000
75 #define DDR_DDR_CDR2 0x00000001
76 #define DDR_SDRAM_CLK_CNTL 0x02000000
77 #define DDR_DDR_ZQ_CNTL 0x89080600
78 #define DDR_CS0_CONFIG_2 0
79 #define DDR_SDRAM_CFG_MEM_EN 0x80000000
80 #define SDRAM_CFG2_D_INIT 0x00000010
81 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
82 #define SDRAM_CFG2_FRC_SR 0x80000000
83 #define SDRAM_CFG_BI 0x00000001
107 #define CONFIG_SPL_TEXT_BASE 0x10000000
108 #define CONFIG_SPL_MAX_SIZE 0x1a000
109 #define CONFIG_SPL_STACK 0x1001d000
110 #define CONFIG_SPL_PAD_TO 0x1c000
111 #define CONFIG_SYS_TEXT_BASE 0x82000000
115 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
116 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
117 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
126 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
128 #define CONFIG_SYS_MONITOR_LEN 0x100000
133 #define CONFIG_SYS_TEXT_BASE 0x40100000
137 #define CONFIG_SYS_TEXT_BASE 0x60100000
141 #define PHYS_SDRAM 0x80000000
144 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
158 #define CONFIG_SYS_FLASH_BASE 0x60000000
161 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
171 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
172 FTIM0_NOR_TEADC(0x5) | \
173 FTIM0_NOR_TAVDS(0x0) | \
174 FTIM0_NOR_TEAHC(0x5))
175 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
176 FTIM1_NOR_TRAD_NOR(0x1A) | \
177 FTIM1_NOR_TSEQRAD_NOR(0x13))
178 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
179 FTIM2_NOR_TCH(0x4) | \
180 FTIM2_NOR_TWP(0x1c) | \
181 FTIM2_NOR_TWPH(0x0e))
182 #define CONFIG_SYS_NOR_FTIM3 0
204 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
207 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
218 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
219 FTIM0_GPCM_TEADC(0xf) | \
220 FTIM0_GPCM_TEAHC(0xf))
221 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
222 FTIM1_GPCM_TRAD(0x3f))
223 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
224 FTIM2_GPCM_TCH(0xf) | \
225 FTIM2_GPCM_TWP(0xff))
226 #define CONFIG_SYS_FPGA_FTIM3 0x0
271 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
284 #define QSPI0_AMBA_BASE 0x40000000
305 #define CONFIG_SYS_I2C_DVI_ADDR 0x39
324 #define TSEC2_PHY_ADDR 0
331 #define TSEC1_PHYIDX 0
332 #define TSEC2_PHYIDX 0
333 #define TSEC3_PHYIDX 0
356 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
366 func(MMC, mmc, 0) \
367 func(USB, usb, 0)
372 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
373 "initrd_high=0xffffffff\0" \
374 "fdt_high=0xffffffff\0" \
375 "fdt_addr=0x64f00000\0" \
376 "kernel_addr=0x65000000\0" \
377 "scriptaddr=0x80000000\0" \
378 "scripthdraddr=0x80080000\0" \
379 "fdtheader_addr_r=0x80100000\0" \
380 "kernelheader_addr_r=0x80200000\0" \
381 "kernel_addr_r=0x81000000\0" \
382 "fdt_addr_r=0x90000000\0" \
383 "ramdisk_addr_r=0xa0000000\0" \
384 "load_addr=0xa0000000\0" \
385 "kernel_size=0x2800000\0" \
387 "boot_scripts=ls1021atwr_boot.scr\0" \
388 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
398 "done\0" \
405 "\0" \
413 "source ${scriptaddr}\0" \
414 "installer=load mmc 0:2 $load_addr " \
416 "bootm $load_addr#ls1021atwr\0" \
419 "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
422 "$kernel_size && bootm $load_addr#$board\0"
425 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
426 "initrd_high=0xffffffff\0" \
427 "fdt_high=0xffffffff\0" \
428 "fdt_addr=0x64f00000\0" \
429 "kernel_addr=0x65000000\0" \
430 "scriptaddr=0x80000000\0" \
431 "scripthdraddr=0x80080000\0" \
432 "fdtheader_addr_r=0x80100000\0" \
433 "kernelheader_addr_r=0x80200000\0" \
434 "kernel_addr_r=0x81000000\0" \
435 "fdt_addr_r=0x90000000\0" \
436 "ramdisk_addr_r=0xa0000000\0" \
437 "load_addr=0xa0000000\0" \
438 "kernel_size=0x2800000\0" \
440 "boot_scripts=ls1021atwr_boot.scr\0" \
441 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
451 "done\0" \
458 "\0" \
466 "source ${scriptaddr}\0" \
467 "installer=load mmc 0:2 $load_addr " \
469 "bootm $load_addr#ls1021atwr\0" \
472 "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
475 "$kernel_size && bootm $load_addr#$board\0"
493 #define CONFIG_SYS_MEMTEST_START 0x80000000
494 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
496 #define CONFIG_SYS_LOAD_ADDR 0x82000000
511 #define CONFIG_SYS_QE_FW_ADDR 0x60940000
519 #define CONFIG_ENV_OFFSET 0x300000
520 #define CONFIG_SYS_MMC_ENV_DEV 0
521 #define CONFIG_ENV_SIZE 0x20000
523 #define CONFIG_ENV_SIZE 0x2000
524 #define CONFIG_ENV_OFFSET 0x300000
525 #define CONFIG_ENV_SECT_SIZE 0x10000
527 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
528 #define CONFIG_ENV_SIZE 0x20000
529 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */