Lines Matching +full:0 +full:x1c000
56 #define CONFIG_SPL_TEXT_BASE 0x10000000
57 #define CONFIG_SPL_MAX_SIZE 0x1a000
58 #define CONFIG_SPL_STACK 0x1001d000
59 #define CONFIG_SPL_PAD_TO 0x1c000
60 #define CONFIG_SYS_TEXT_BASE 0x82000000
64 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
65 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
66 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
67 #define CONFIG_SYS_MONITOR_LEN 0xc0000
71 #define CONFIG_SYS_TEXT_BASE 0x40100000
78 #define CONFIG_SPL_TEXT_BASE 0x10000000
79 #define CONFIG_SPL_MAX_SIZE 0x1a000
80 #define CONFIG_SPL_STACK 0x1001d000
81 #define CONFIG_SPL_PAD_TO 0x1c000
82 #define CONFIG_SYS_TEXT_BASE 0x82000000
90 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
91 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
92 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
93 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
94 #define CONFIG_SYS_MONITOR_LEN 0x80000
98 #define CONFIG_SYS_TEXT_BASE 0x60100000
104 #define SPD_EEPROM_ADDRESS 0x51
105 #define CONFIG_SYS_SPD_BUS_NUM 0
114 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
120 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
134 #define CONFIG_SYS_FLASH_BASE 0x60000000
137 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
142 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
144 + 0x8000000) | \
152 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
153 FTIM0_NOR_TEADC(0x5) | \
154 FTIM0_NOR_TEAHC(0x5))
155 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
156 FTIM1_NOR_TRAD_NOR(0x1a) | \
157 FTIM1_NOR_TSEQRAD_NOR(0x13))
158 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
159 FTIM2_NOR_TCH(0x4) | \
160 FTIM2_NOR_TWPH(0xe) | \
161 FTIM2_NOR_TWP(0x1c))
162 #define CONFIG_SYS_NOR_FTIM3 0
179 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
186 #define CONFIG_SYS_NAND_BASE 0x7e800000
189 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
206 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
207 FTIM0_NAND_TWP(0x18) | \
208 FTIM0_NAND_TWCHT(0x7) | \
209 FTIM0_NAND_TWH(0xa))
210 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
211 FTIM1_NAND_TWBE(0x39) | \
212 FTIM1_NAND_TRR(0xe) | \
213 FTIM1_NAND_TRP(0x18))
214 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
215 FTIM2_NAND_TREH(0xa) | \
216 FTIM2_NAND_TWHRE(0x1e))
217 #define CONFIG_SYS_NAND_FTIM3 0x0
231 #define QIXIS_BASE 0x7fb00000
233 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
235 #define QIXIS_LBMAP_MASK 0x0f
236 #define QIXIS_LBMAP_SHIFT 0
237 #define QIXIS_LBMAP_DFLTBANK 0x00
238 #define QIXIS_LBMAP_ALTBANK 0x04
239 #define QIXIS_PWR_CTL 0x21
240 #define QIXIS_PWR_CTL_POWEROFF 0x80
241 #define QIXIS_RST_CTL_RESET 0x44
242 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
243 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
244 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
245 #define QIXIS_CTL_SYS 0x5
246 #define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
247 #define QIXIS_CTL_SYS_EVTSW_IRQ 0x04
248 #define QIXIS_RST_FORCE_3 0x45
249 #define QIXIS_RST_FORCE_3_PCIESLOT1 0x80
250 #define QIXIS_PWR_CTL2 0x21
251 #define QIXIS_PWR_CTL2_PCTL 0x2
253 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
266 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
267 FTIM0_GPCM_TEADC(0xe) | \
268 FTIM0_GPCM_TEAHC(0xe))
269 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
270 FTIM1_GPCM_TRAD(0x1f))
271 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
272 FTIM2_GPCM_TCH(0xe) | \
273 FTIM2_GPCM_TWP(0xf0))
274 #define CONFIG_SYS_FPGA_FTIM3 0x0
371 #define I2C_MUX_PCA_ADDR_PRI 0x77
372 #define I2C_MUX_CH_DEFAULT 0x8
373 #define I2C_MUX_CH_CH7301 0xC
383 #define QSPI0_AMBA_BASE 0x40000000
423 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
424 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66
425 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
451 #define TSEC1_PHYIDX 0
452 #define TSEC2_PHYIDX 0
453 #define TSEC3_PHYIDX 0
464 #define SGMII_RISER_PHY_OFFSET 0x1b
485 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
494 #define CONFIG_SYS_QE_FW_ADDR 0x60940000
498 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
499 "fdt_high=0xffffffff\0" \
500 "initrd_high=0xffffffff\0" \
501 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
504 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
505 "fdt_high=0xffffffff\0" \
506 "initrd_high=0xffffffff\0" \
507 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
516 #define CONFIG_SYS_MEMTEST_START 0x80000000
517 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
519 #define CONFIG_SYS_LOAD_ADDR 0x82000000
540 #define CONFIG_ENV_OFFSET 0x300000
541 #define CONFIG_SYS_MMC_ENV_DEV 0
542 #define CONFIG_ENV_SIZE 0x2000
544 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
545 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
546 #define CONFIG_ENV_SECT_SIZE 0x10000
548 #define CONFIG_ENV_SIZE 0x2000
551 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
552 #define CONFIG_ENV_SIZE 0x2000
553 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */