Lines Matching +full:0 +full:x1c000
37 #define DDR_SDRAM_CFG 0x470c0008
38 #define DDR_CS0_BNDS 0x008000bf
39 #define DDR_CS0_CONFIG 0x80014302
40 #define DDR_TIMING_CFG_0 0x50550004
41 #define DDR_TIMING_CFG_1 0xbcb38c56
42 #define DDR_TIMING_CFG_2 0x0040d120
43 #define DDR_TIMING_CFG_3 0x010e1000
44 #define DDR_TIMING_CFG_4 0x00000001
45 #define DDR_TIMING_CFG_5 0x03401400
46 #define DDR_SDRAM_CFG_2 0x00401010
47 #define DDR_SDRAM_MODE 0x00061c60
48 #define DDR_SDRAM_MODE_2 0x00180000
49 #define DDR_SDRAM_INTERVAL 0x18600618
50 #define DDR_DDR_WRLVL_CNTL 0x8655f605
51 #define DDR_DDR_WRLVL_CNTL_2 0x05060607
52 #define DDR_DDR_WRLVL_CNTL_3 0x05050505
53 #define DDR_DDR_CDR1 0x80040000
54 #define DDR_DDR_CDR2 0x00000001
55 #define DDR_SDRAM_CLK_CNTL 0x02000000
56 #define DDR_DDR_ZQ_CNTL 0x89080600
57 #define DDR_CS0_CONFIG_2 0
58 #define DDR_SDRAM_CFG_MEM_EN 0x80000000
59 #define SDRAM_CFG2_D_INIT 0x00000010
60 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
61 #define SDRAM_CFG2_FRC_SR 0x80000000
62 #define SDRAM_CFG_BI 0x00000001
81 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
83 #define CONFIG_SPL_TEXT_BASE 0x10000000
84 #define CONFIG_SPL_MAX_SIZE 0x1a000
85 #define CONFIG_SPL_STACK 0x1001d000
86 #define CONFIG_SPL_PAD_TO 0x1c000
87 #define CONFIG_SYS_TEXT_BASE 0x82000000
91 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
92 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
93 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
94 #define CONFIG_SYS_MONITOR_LEN 0x80000
98 #define CONFIG_SYS_TEXT_BASE 0x40010000
103 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
127 #define CONFIG_SYS_EEPROM_BUS_NUM 0
128 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
142 #define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440
157 #define QSPI0_AMBA_BASE 0x40000000
189 #define TSEC1_PHYIDX 0
190 #define TSEC2_PHYIDX 0
224 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
233 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
234 "initrd_high=0xffffffff\0" \
235 "fdt_high=0xffffffff\0"
247 #define CONFIG_SYS_LOAD_ADDR 0x82000000
263 #define CONFIG_SYS_QE_FW_ADDR 0x67f40000
272 #define CONFIG_ENV_OFFSET 0x100000
273 #define CONFIG_SYS_MMC_ENV_DEV 0
274 #define CONFIG_ENV_SIZE 0x2000
276 #define CONFIG_ENV_SIZE 0x2000
277 #define CONFIG_ENV_OFFSET 0x100000
278 #define CONFIG_ENV_SECT_SIZE 0x10000