Lines Matching +full:0 +full:xfb000000
11 #define CONFIG_SYS_TEXT_BASE 0xfff40000
13 #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0"
27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
47 #define CONFIG_ENV_SPI_BUS 0
48 #define CONFIG_ENV_SPI_CS 0
50 #define CONFIG_ENV_SPI_MODE 0
51 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB for u-boot */
52 #define CONFIG_ENV_SIZE 0x004000 /* 16K env */
53 #define CONFIG_ENV_SECT_SIZE 0x010000
54 #define CONFIG_ENV_OFFSET_REDUND 0x110000
55 #define CONFIG_ENV_TOTAL_SIZE 0x020000
62 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
83 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
88 #define CONFIG_SYS_DCSRBAR 0xf0000000
89 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
95 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
104 #define CONFIG_SYS_SPD_BUS_NUM 0
105 #define SPD_EEPROM_ADDRESS 0x54
108 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
125 #define CONFIG_KM_ROOTFSSIZE 0x0
127 #define CONFIG_KM_PNVRAM 0x80000
129 #define CONFIG_KM_PHRAM 0x100000
132 #define CONFIG_KM_RESERVED_PRAM 0x1000
137 #define CONFIG_KM_CRAMFS_ADDR 0x2000000
138 #define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */
139 #define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */
150 #define CONFIG_SYS_NAND_BASE 0xffa00000
151 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
174 #define CONFIG_SYS_QRIO_BASE 0xfb000000
175 #define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull
195 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_QRIO_BASE + 0x20)
207 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
208 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
214 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
231 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
233 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
234 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
235 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
236 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
251 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
252 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
253 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
254 {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
255 {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
271 #define CONFIG_SF_DEFAULT_MODE 0
275 * Memory space is mapped 1-1, but I/O space must start from 0.
279 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
280 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
281 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
282 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
283 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
284 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
285 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
286 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
289 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
290 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
291 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
292 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
293 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000
294 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
295 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull
296 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
301 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
302 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
303 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
304 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
305 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
311 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
313 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
314 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
315 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
316 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
317 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
323 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
328 * env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
329 * ucode is stored after env, so we got 0x120000.
332 #define CONFIG_SYS_FMAN_FW_ADDR 0x120000
333 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
334 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
345 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11
391 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
409 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
412 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
413 "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \
414 "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.pbl\0" \
416 "sf probe 0;sf erase 0 +${filesize};" \
417 "sf write ${load_addr_r} 0 ${filesize};\0" \
418 "set_fdthigh=true\0" \
419 "checkfdt=true\0" \
423 "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \
424 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
425 "usb_dr_mode=host\0"
428 "newenv=sf probe 0;" \
430 __stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
434 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
442 "EEprom_ivm=pca9547:70:9\0" \