Lines Matching +full:0 +full:xe8000000

21 #define CONFIG_KM_DEF_ARCH	"arch=ppc_82xx\0"
30 #define CONFIG_SYS_QE_FW_ADDR   0xF00C0000
36 /* 0x14000180 SICR_1 */
37 #define CONFIG_SYS_SICRL (0			\
54 /* 0x00080400 SICR_2 */
55 #define CONFIG_SYS_SICRH (0			\
71 #define CONFIG_SYS_GPR1  0x50008060
73 #define CONFIG_SYS_GP1DIR 0x00000000
74 #define CONFIG_SYS_GP1ODR 0x00000000
75 #define CONFIG_SYS_GP2DIR 0xFF000000
76 #define CONFIG_SYS_GP2ODR 0x00000000
106 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000007f
112 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
114 #define CONFIG_SYS_DDR_INTERVAL	((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
115 				 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
123 #define CONFIG_SYS_DDR_MODE	0x47860242
124 #define CONFIG_SYS_DDR_MODE2	0x8080c000
130 				 (0 << TIMING_CFG0_WWT_SHIFT) | \
131 				 (0 << TIMING_CFG0_RRT_SHIFT) | \
132 				 (0 << TIMING_CFG0_WRT_SHIFT) | \
133 				 (0 << TIMING_CFG0_RWT_SHIFT))
149 				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
152 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
154 #define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
163 #define CONFIG_SYS_LCRR_DBYP	0x80000000
164 #define CONFIG_SYS_LCRR_EADC	0x00010000
165 #define CONFIG_SYS_LCRR_CLKDIV	0x00000002
167 #define CONFIG_SYS_LBC_LBCR	0x00000000
172 #define CONFIG_SYS_IBAT7L	(0)
173 #define CONFIG_SYS_IBAT7U	(0)