Lines Matching +full:0 +full:x7f
21 #define CONFIG_SYS_TEXT_BASE 0xFE000000
84 SICRH_TSOBI2_V2P5) /* 0x0037f103 */
90 SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */
95 #define CONFIG_SYS_IMMR 0xE0000000
101 #define CONFIG_FSL_SERDES1 0xe3000
113 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
122 /* 0x7b880001 */
130 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
136 /* 0x80010102 */
137 #define CONFIG_SYS_DDR_TIMING_3 0
138 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
139 | (0 << TIMING_CFG0_WRT_SHIFT) \
140 | (0 << TIMING_CFG0_RRT_SHIFT) \
141 | (0 << TIMING_CFG0_WWT_SHIFT) \
146 /* 0x00260802 */
155 /* 0x26279222 */
156 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
163 /* 0x021848c5 */
164 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
165 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
166 /* 0x08240100 */
170 /* 0x43100000 */
172 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
173 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
174 | (0x0242 << SDRAM_MODE_SD_SHIFT))
175 /* ODT 150ohm CL=4, AL=0 on SDRAM */
176 #define CONFIG_SYS_DDR_MODE2 0x00000000
181 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
182 #define CONFIG_SYS_MEMTEST_END 0x07f00000
196 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
197 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
206 #define CONFIG_SYS_LBC_LBCR 0x00040000
219 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
249 #define CONFIG_SYS_FPGA0_BASE 0xE0600000
270 #define CONFIG_SYS_FPGA_DONE(k) 0x0010
285 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
290 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
291 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
299 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
300 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
308 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
311 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
314 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
317 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
323 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
326 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
329 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
332 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
340 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
343 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
346 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
349 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
352 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
355 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
358 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
361 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
366 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
369 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
372 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
375 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
381 #define CONFIG_HRCON_FANS { {10, 0x4c}, {11, 0x4c}, \
382 {12, 0x4c} }
386 #define CONFIG_HRCON_FANS { {6, 0x4c}, {7, 0x4c}, \
387 {8, 0x4c} }
398 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
399 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
406 fpga_control_set(I2C_FPGA_IDX, 0x0004); \
408 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
409 } while (0)
415 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
422 } while (0)
429 } while (0)
443 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
453 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
454 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
455 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
456 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
457 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
458 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
459 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
460 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
461 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
469 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
476 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
486 #define TSEC1_PHYIDX 0
489 /* Options are: eTSEC[0-1] */
498 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
499 #define CONFIG_ENV_SIZE 0x2000
503 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
520 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
537 #define CONFIG_SYS_HID0_INIT 0x000000000
600 "netdev=eth0\0" \
601 "consoledev=ttyS1\0" \
602 "u-boot=u-boot.bin\0" \
603 "kernel_addr=1000000\0" \
604 "fdt_addr=C00000\0" \
605 "fdtfile=hrcon.dtb\0" \
606 "load=tftp ${loadaddr} ${u-boot}\0" \
610 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
611 "upd=run load update\0" \
625 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
626 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \