Lines Matching +full:0 +full:xfdd00000
30 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
47 #define CONFIG_SYS_TEXT_BASE 0xeff40000
62 #define CONFIG_SYS_MMC_ENV_DEV 0
63 #define CONFIG_ENV_SIZE 0x2000
77 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
89 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
90 #define CONFIG_SYS_MEMTEST_END 0x00400000
98 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
106 #define CONFIG_SYS_DCSRBAR 0xf0000000
107 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
114 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
123 #define SPD_EEPROM_ADDRESS1 0x51
124 #define SPD_EEPROM_ADDRESS2 0x52
131 #define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */
133 #define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull
138 #define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */
140 #define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull
153 #define CONFIG_SYS_OR0_PRELIM 0xfff00010
154 #define CONFIG_SYS_OR1_PRELIM 0xfff00010
170 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
172 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
180 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
183 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
198 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
203 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
204 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
205 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
206 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
214 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
215 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
217 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
218 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
220 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
221 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
223 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
224 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
228 #define CONFIG_SYS_EEPROM_BUS_NUM 0
230 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
234 #define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57
235 #define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2
236 #define CONFIG_SYS_I2C_MAC2_BUS 0
237 #define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50
238 #define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa
242 #define CONFIG_SYS_I2C_RTC_ADDR 0x6f
250 * Memory space is mapped 1-1, but I/O space must start from 0.
254 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
256 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
257 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
259 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
260 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
262 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
263 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
264 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
266 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
268 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
270 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
273 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
275 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
276 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
278 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
279 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
281 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
282 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
283 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
285 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
287 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
289 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
292 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
294 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
295 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
297 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
298 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
300 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
301 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
302 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
304 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
306 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
308 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
311 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
312 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
313 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
314 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
315 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
316 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
321 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
323 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
327 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
328 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
329 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
335 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
337 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
339 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
343 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
344 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
345 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
351 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
356 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
358 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
363 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
364 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
430 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
460 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
461 "netdev=eth0\0" \
462 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
463 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
464 "consoledev=ttyS0\0" \
465 "ramdiskaddr=2000000\0" \
466 "fdtaddr=1e00000\0" \
467 "bdev=sda3\0"