include/configs/T4240QDS.h

2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
4  * SPDX-License-Identifier:	GPL-2.0+
25 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
38 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
53 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
111 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
217 					FTIM2_GPCM_TCH(0x8) | \
235 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
328 #define I2C_MUX_CH_DEFAULT	0x8
349  * for slave u-boot IMAGE instored in master memory space,
369  * SRIO_PCIE_BOOT - SLAVE
377  * eSPI - Enhanced SPI
427  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
438  * Slave has no ucode locally, it can fetch this from remote. When implementing
440  * space, the address can be mapped from slave TLB->slave LAW->
441  * slave SRIO or PCIE outbound window->master inbound window->
442  * master LAW->the ucode address in master's memory space.
513  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
514  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
516  * See doc/README.fsl-ddr for details.
546 	"setenv bootargs config-addr=0x60000000; "	\
547 	"bootm 0x01000000 - 0x00f00000"
552 	"cpu 1 release 0x01000000 - - -;"		\
553 	"cpu 2 release 0x01000000 - - -;"		\
554 	"cpu 3 release 0x01000000 - - -;"		\
555 	"cpu 4 release 0x01000000 - - -;"		\
556 	"cpu 5 release 0x01000000 - - -;"		\
557 	"cpu 6 release 0x01000000 - - -;"		\
558 	"cpu 7 release 0x01000000 - - -;"		\
574 	"bootm $loadaddr - $fdtaddr"
583 	"bootm $loadaddr - $fdtaddr"