Lines Matching +full:0 +full:x00200000
36 #define CONFIG_SYS_TEXT_BASE 0x00201000
37 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
38 #define CONFIG_SPL_PAD_TO 0x40000
39 #define CONFIG_SPL_MAX_SIZE 0x28000
40 #define RESET_VECTOR_OFFSET 0x27FFC
41 #define BOOT_PAGE_OFFSET 0x27000
50 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
51 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
59 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
74 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
77 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
78 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
93 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
95 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
96 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
100 #define CONFIG_SYS_TEXT_BASE 0xeff40000
104 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
115 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
118 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
119 #define CONFIG_SYS_MEMTEST_END 0x00400000
130 #define CONFIG_ENV_SPI_BUS 0
131 #define CONFIG_ENV_SPI_CS 0
133 #define CONFIG_ENV_SPI_MODE 0
134 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
135 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
136 #define CONFIG_ENV_SECT_SIZE 0x10000
139 #define CONFIG_SYS_MMC_ENV_DEV 0
140 #define CONFIG_ENV_SIZE 0x2000
141 #define CONFIG_ENV_OFFSET (512 * 0x800)
144 #define CONFIG_ENV_SIZE 0x2000
147 #define CONFIG_ENV_ADDR 0xffe20000
148 #define CONFIG_ENV_SIZE 0x2000
150 #define CONFIG_ENV_SIZE 0x2000
153 #define CONFIG_ENV_SIZE 0x2000
154 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
168 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
179 #define CONFIG_SYS_DCSRBAR 0xf0000000
180 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
185 #define CONFIG_SYS_EEPROM_BUS_NUM 0
186 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
193 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
199 #define CONFIG_SYS_SPD_BUS_NUM 0
201 #define SPD_EEPROM_ADDRESS1 0x51
202 #define SPD_EEPROM_ADDRESS2 0x52
209 #define CONFIG_SYS_FLASH_BASE 0xe8000000
210 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
211 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
221 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
222 FTIM0_NOR_TEADC(0x5) | \
223 FTIM0_NOR_TEAHC(0x5))
224 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
225 FTIM1_NOR_TRAD_NOR(0x1A) |\
226 FTIM1_NOR_TSEQRAD_NOR(0x13))
227 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
228 FTIM2_NOR_TCH(0x4) | \
229 FTIM2_NOR_TWPH(0x0E) | \
230 FTIM2_NOR_TWP(0x1c))
231 #define CONFIG_SYS_NOR_FTIM3 0x0
244 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
245 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
246 #define CONFIG_SYS_CSPR2_EXT (0xf)
252 #define CONFIG_SYS_CSOR2 0x0
255 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
256 FTIM0_GPCM_TEADC(0x0e) | \
257 FTIM0_GPCM_TEAHC(0x0e))
258 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
259 FTIM1_GPCM_TRAD(0x1f))
260 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
261 FTIM2_GPCM_TCH(0x8) | \
262 FTIM2_GPCM_TWP(0x1f))
263 #define CONFIG_SYS_CS2_FTIM3 0x0
267 #define CONFIG_SYS_NAND_BASE 0xff800000
268 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
270 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
288 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
289 FTIM0_NAND_TWP(0x18) | \
290 FTIM0_NAND_TWCHT(0x07) | \
291 FTIM0_NAND_TWH(0x0a))
292 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
293 FTIM1_NAND_TWBE(0x39) | \
294 FTIM1_NAND_TRR(0x0e) | \
295 FTIM1_NAND_TRP(0x18))
296 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
297 FTIM2_NAND_TREH(0x0a) | \
298 FTIM2_NAND_TWHRE(0x1e))
299 #define CONFIG_SYS_NAND_FTIM3 0x0
359 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
360 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
361 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
366 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
379 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
382 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
383 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
384 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
385 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
392 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
393 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
394 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
395 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
396 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
397 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
398 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
399 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
404 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
405 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
406 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
407 #define I2C_MUX_CH_DEFAULT 0x8
409 #define I2C_MUX_CH_VOL_MONITOR 0xa
424 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
425 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
426 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
427 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
428 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
429 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
434 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
435 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
436 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
437 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
442 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
443 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
444 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
447 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
448 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
454 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
456 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
465 #define CONFIG_SF_DEFAULT_MODE 0
470 * Memory space is mapped 1-1, but I/O space must start from 0.
479 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
480 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
481 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
482 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
483 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
484 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
485 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
486 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
489 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
490 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
491 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
492 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
493 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
494 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
495 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
496 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
499 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
500 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
501 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
502 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
503 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
504 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
505 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
506 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
509 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
510 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
511 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
512 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
513 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
514 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
515 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
527 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
528 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
529 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
530 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
531 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
537 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
539 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
540 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
541 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
542 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
543 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
549 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
561 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
562 * env, so we got 0x110000.
566 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
567 #define CONFIG_CORTINA_FW_ADDR 0x120000
571 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
573 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
577 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
578 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0)
595 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
596 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000
600 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
601 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000
603 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
604 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
613 #define CONFIG_CORTINA_FW_LENGTH 0x40000
614 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
615 #define RGMII_PHY2_ADDR 0x02
616 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
617 #define CORTINA_PHY_ADDR2 0x0d
618 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */
619 #define FM1_10GEC4_PHY_ADDR 0x01
685 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
715 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
716 "netdev=eth0\0" \
717 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
718 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
724 "cmp.b $loadaddr $ubootaddr $filesize\0" \
725 "consoledev=ttyS0\0" \
726 "ramdiskaddr=2000000\0" \
727 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
728 "fdtaddr=1e00000\0" \
729 "fdtfile=t2080rdb/t2080rdb.dtb\0" \
730 "bdev=sda3\0"
739 "cpu 1 release 0x29000000 - - -;" \
740 "cpu 2 release 0x29000000 - - -;" \
741 "cpu 3 release 0x29000000 - - -;" \
742 "cpu 4 release 0x29000000 - - -;" \
743 "cpu 5 release 0x29000000 - - -;" \
744 "cpu 6 release 0x29000000 - - -;" \
745 "cpu 7 release 0x29000000 - - -;" \
746 "go 0x29000000"
749 "setenv bootargs config-addr=0x60000000; " \
750 "bootm 0x01000000 - 0x00f00000"
755 "cpu 1 release 0x01000000 - - -;" \
756 "cpu 2 release 0x01000000 - - -;" \
757 "cpu 3 release 0x01000000 - - -;" \
758 "cpu 4 release 0x01000000 - - -;" \
759 "cpu 5 release 0x01000000 - - -;" \
760 "cpu 6 release 0x01000000 - - -;" \
761 "cpu 7 release 0x01000000 - - -;" \
762 "go 0x01000000"
767 "setenv ramdiskaddr 0x02000000;" \
768 "setenv fdtaddr 0x00c00000;" \
769 "setenv loadaddr 0x1000000;" \