Lines Matching +full:0 +full:xfdd00000
42 #define CONFIG_SYS_TEXT_BASE 0x00201000
43 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
44 #define CONFIG_SPL_PAD_TO 0x40000
45 #define CONFIG_SPL_MAX_SIZE 0x28000
46 #define RESET_VECTOR_OFFSET 0x27FFC
47 #define BOOT_PAGE_OFFSET 0x27000
56 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
57 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
69 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
72 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
73 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
88 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
91 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
92 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
111 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
113 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
114 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
118 #define CONFIG_SYS_TEXT_BASE 0xeff40000
122 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
133 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
144 #define CONFIG_ENV_SPI_BUS 0
145 #define CONFIG_ENV_SPI_CS 0
147 #define CONFIG_ENV_SPI_MODE 0
148 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
149 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
150 #define CONFIG_ENV_SECT_SIZE 0x10000
153 #define CONFIG_SYS_MMC_ENV_DEV 0
154 #define CONFIG_ENV_SIZE 0x2000
155 #define CONFIG_ENV_OFFSET (512 * 0x800)
158 #define CONFIG_ENV_SIZE 0x2000
161 #define CONFIG_ENV_ADDR 0xffe20000
162 #define CONFIG_ENV_SIZE 0x2000
164 #define CONFIG_ENV_SIZE 0x2000
167 #define CONFIG_ENV_SIZE 0x2000
168 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
182 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
193 #define CONFIG_SYS_DCSRBAR 0xf0000000
194 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
199 #define CONFIG_SYS_EEPROM_BUS_NUM 0
200 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
207 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
214 #define CONFIG_SYS_SPD_BUS_NUM 0
216 #define SPD_EEPROM_ADDRESS1 0x51
217 #define SPD_EEPROM_ADDRESS2 0x52
224 #define CONFIG_SYS_FLASH_BASE 0xe0000000
225 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
226 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
228 + 0x8000000) | \
232 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
241 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
242 FTIM0_NOR_TEADC(0x5) | \
243 FTIM0_NOR_TEAHC(0x5))
244 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
245 FTIM1_NOR_TRAD_NOR(0x1A) |\
246 FTIM1_NOR_TSEQRAD_NOR(0x13))
247 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
248 FTIM2_NOR_TCH(0x4) | \
249 FTIM2_NOR_TWPH(0x0E) | \
250 FTIM2_NOR_TWP(0x1c))
251 #define CONFIG_SYS_NOR_FTIM3 0x0
263 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
266 #define QIXIS_BASE 0xffdf0000
268 #define QIXIS_LBMAP_MASK 0x0f
269 #define QIXIS_LBMAP_SHIFT 0
270 #define QIXIS_LBMAP_DFLTBANK 0x00
271 #define QIXIS_LBMAP_ALTBANK 0x04
272 #define QIXIS_LBMAP_NAND 0x09
273 #define QIXIS_LBMAP_SD 0x00
274 #define QIXIS_RCW_SRC_NAND 0x104
275 #define QIXIS_RCW_SRC_SD 0x040
276 #define QIXIS_RST_CTL_RESET 0x83
277 #define QIXIS_RST_FORCE_MEM 0x1
278 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
279 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
280 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
281 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
283 #define CONFIG_SYS_CSPR3_EXT (0xf)
289 #define CONFIG_SYS_CSOR3 0x0
291 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
292 FTIM0_GPCM_TEADC(0x0e) | \
293 FTIM0_GPCM_TEAHC(0x0e))
294 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
295 FTIM1_GPCM_TRAD(0x3f))
296 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
297 FTIM2_GPCM_TCH(0x8) | \
298 FTIM2_GPCM_TWP(0x1f))
299 #define CONFIG_SYS_CS3_FTIM3 0x0
303 #define CONFIG_SYS_NAND_BASE 0xff800000
304 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
306 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
324 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
325 FTIM0_NAND_TWP(0x18) | \
326 FTIM0_NAND_TWCHT(0x07) | \
327 FTIM0_NAND_TWH(0x0a))
328 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
329 FTIM1_NAND_TWBE(0x39) | \
330 FTIM1_NAND_TRR(0x0e) | \
331 FTIM1_NAND_TRP(0x18))
332 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
333 FTIM2_NAND_TREH(0x0a) | \
334 FTIM2_NAND_TWHRE(0x1e))
335 #define CONFIG_SYS_NAND_FTIM3 0x0
411 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
412 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
413 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
418 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
431 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
434 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
435 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
436 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
437 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
444 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
445 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
446 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
447 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
448 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
449 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
450 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
451 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
456 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
457 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
458 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
459 #define I2C_MUX_CH_DEFAULT 0x8
461 #define I2C_MUX_CH_VOL_MONITOR 0xa
464 #define I2C_VOL_MONITOR_ADDR 0x40
465 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
466 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
482 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
483 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
484 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
485 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
486 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
487 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
492 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
493 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
494 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
495 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
500 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
501 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
502 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
505 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
506 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
512 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
514 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
526 #define CONFIG_SF_DEFAULT_MODE 0
531 * Memory space is mapped 1-1, but I/O space must start from 0.
541 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
542 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
543 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
544 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
545 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
546 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
547 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
548 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
551 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
552 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
553 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
554 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
555 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
556 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
557 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
558 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
561 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
562 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
563 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
564 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
565 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
566 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
567 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
568 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
571 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
572 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
573 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
574 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
575 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
576 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
577 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
589 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
590 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
591 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
592 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
593 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
599 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
601 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
602 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
603 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
604 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
605 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
611 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
623 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
624 * env, so we got 0x110000.
627 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
630 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
632 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
635 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
648 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
651 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
653 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
654 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
663 #define RGMII_PHY1_ADDR 0x1
664 #define RGMII_PHY2_ADDR 0x2
665 #define FM1_10GEC1_PHY_ADDR 0x3
666 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
667 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
668 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
669 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
720 "spi0=spife110000.0"
723 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
739 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
769 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
770 "netdev=eth0\0" \
771 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
772 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
778 "cmp.b $loadaddr $ubootaddr $filesize\0" \
779 "consoledev=ttyS0\0" \
780 "ramdiskaddr=2000000\0" \
781 "ramdiskfile=t2080qds/ramdisk.uboot\0" \
782 "fdtaddr=1e00000\0" \
783 "fdtfile=t2080qds/t2080qds.dtb\0" \
784 "bdev=sda3\0"
793 "cpu 1 release 0x29000000 - - -;" \
794 "cpu 2 release 0x29000000 - - -;" \
795 "cpu 3 release 0x29000000 - - -;" \
796 "cpu 4 release 0x29000000 - - -;" \
797 "cpu 5 release 0x29000000 - - -;" \
798 "cpu 6 release 0x29000000 - - -;" \
799 "cpu 7 release 0x29000000 - - -;" \
800 "go 0x29000000"
803 "setenv bootargs config-addr=0x60000000; " \
804 "bootm 0x01000000 - 0x00f00000"
809 "cpu 1 release 0x01000000 - - -;" \
810 "cpu 2 release 0x01000000 - - -;" \
811 "cpu 3 release 0x01000000 - - -;" \
812 "cpu 4 release 0x01000000 - - -;" \
813 "cpu 5 release 0x01000000 - - -;" \
814 "cpu 6 release 0x01000000 - - -;" \
815 "cpu 7 release 0x01000000 - - -;" \
816 "go 0x01000000"
821 "setenv ramdiskaddr 0x02000000;" \
822 "setenv fdtaddr 0x00c00000;" \
823 "setenv loadaddr 0x1000000;" \