Lines Matching +full:0 +full:xfdd00000
26 #define CONFIG_SYS_TEXT_BASE 0x30001000
27 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
28 #define CONFIG_SPL_PAD_TO 0x40000
29 #define CONFIG_SPL_MAX_SIZE 0x28000
35 #define RESET_VECTOR_OFFSET 0x27FFC
36 #define BOOT_PAGE_OFFSET 0x27000
50 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
51 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
78 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
112 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
115 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
116 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
155 #define CONFIG_SYS_TEXT_BASE 0xeff40000
159 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
183 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
184 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
185 #define CONFIG_ENV_SECT_SIZE 0x10000
188 #define CONFIG_SYS_MMC_ENV_DEV 0
189 #define CONFIG_ENV_SIZE 0x2000
190 #define CONFIG_ENV_OFFSET (512 * 0x800)
197 #define CONFIG_ENV_SIZE 0x2000
201 #define CONFIG_ENV_SIZE 0x2000
202 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
218 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
226 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
227 #define CONFIG_SYS_MEMTEST_END 0x00400000
233 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
239 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
250 #define CONFIG_SYS_DCSRBAR 0xf0000000
251 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
257 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
265 #define CONFIG_SYS_SPD_BUS_NUM 0
266 #define SPD_EEPROM_ADDRESS 0x51
273 #define CONFIG_SYS_FLASH_BASE 0xe8000000
274 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
276 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
286 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
290 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
291 FTIM0_NOR_TEADC(0x5) | \
292 FTIM0_NOR_TEAHC(0x5))
293 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
294 FTIM1_NOR_TRAD_NOR(0x1A) |\
295 FTIM1_NOR_TSEQRAD_NOR(0x13))
296 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
297 FTIM2_NOR_TCH(0x4) | \
298 FTIM2_NOR_TWPH(0x0E) | \
299 FTIM2_NOR_TWP(0x1c))
300 #define CONFIG_SYS_NOR_FTIM3 0x0
314 #define CPLD_LBMAP_MASK 0x3F
315 #define CPLD_BANK_SEL_MASK 0x07
316 #define CPLD_BANK_OVERRIDE 0x40
317 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
318 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
319 #define CPLD_LBMAP_RESET 0xFF
320 #define CPLD_LBMAP_SHIFT 0x03
323 #define CPLD_DIU_SEL_DFP 0x80
325 #define CPLD_DIU_SEL_DFP 0xc0
329 #define CPLD_INT_MASK_ALL 0xFF
330 #define CPLD_INT_MASK_THERM 0x80
331 #define CPLD_INT_MASK_DVI_DFP 0x40
332 #define CPLD_INT_MASK_QSGMII1 0x20
333 #define CPLD_INT_MASK_QSGMII2 0x10
334 #define CPLD_INT_MASK_SGMI1 0x08
335 #define CPLD_INT_MASK_SGMI2 0x04
336 #define CPLD_INT_MASK_TDMR1 0x02
337 #define CPLD_INT_MASK_TDMR2 0x01
340 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
341 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
342 #define CONFIG_SYS_CSPR2_EXT (0xf)
348 #define CONFIG_SYS_CSOR2 0x0
350 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
351 FTIM0_GPCM_TEADC(0x0e) | \
352 FTIM0_GPCM_TEAHC(0x0e))
353 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
354 FTIM1_GPCM_TRAD(0x1f))
355 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
356 FTIM2_GPCM_TCH(0x8) | \
357 FTIM2_GPCM_TWP(0x1f))
358 #define CONFIG_SYS_CS2_FTIM3 0x0
362 #define CONFIG_SYS_NAND_BASE 0xff800000
363 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
365 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
383 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
384 FTIM0_NAND_TWP(0x18) | \
385 FTIM0_NAND_TWCHT(0x07) | \
386 FTIM0_NAND_TWH(0x0a))
387 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
388 FTIM1_NAND_TWBE(0x39) | \
389 FTIM1_NAND_TRR(0x0e) | \
390 FTIM1_NAND_TRP(0x18))
391 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
392 FTIM2_NAND_TREH(0x0a) | \
393 FTIM2_NAND_TWHRE(0x1e))
394 #define CONFIG_SYS_NAND_FTIM3 0x0
462 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
463 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
464 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
469 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
485 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
490 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
491 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
492 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
493 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
501 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
514 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
515 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
516 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
517 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
518 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
519 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
520 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
521 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
524 #define I2C_MUX_PCA_ADDR 0x70
525 #define I2C_MUX_CH_DEFAULT 0x8
531 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
532 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
539 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
542 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
550 #define CONFIG_SF_DEFAULT_MODE 0
551 #define CONFIG_ENV_SPI_BUS 0
552 #define CONFIG_ENV_SPI_CS 0
554 #define CONFIG_ENV_SPI_MODE 0
558 * Memory space is mapped 1-1, but I/O space must start from 0.
564 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
565 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
566 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
567 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
568 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
569 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
570 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
571 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
576 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
577 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
578 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
579 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
580 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
581 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
582 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
583 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
588 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
589 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
590 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
591 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
592 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
593 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
594 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
595 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
600 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
601 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
602 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
603 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
604 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
605 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
606 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
607 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
648 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
649 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
650 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
651 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
652 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
658 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
660 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
661 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
662 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
663 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
664 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
670 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
681 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
682 * env, so we got 0x110000.
685 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
688 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
690 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
693 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
699 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
703 #define CONFIG_SYS_QE_FW_ADDR 0x130000
705 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
709 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
712 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
713 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
724 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
726 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
728 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
729 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
730 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
734 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
735 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
737 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
738 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
745 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
746 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
748 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
749 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
769 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
789 "spi0=spife110000.0"
793 "128k(dtb),96m(fs),-(user);spife110000.0:" \
831 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
832 "netdev=eth0\0" \
833 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \
834 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
835 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
841 "cmp.b $loadaddr $ubootaddr $filesize\0" \
842 "consoledev=ttyS0\0" \
843 "ramdiskaddr=2000000\0" \
844 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
845 "fdtaddr=1e00000\0" \
846 "fdtfile=" __stringify(FDTFILE) "\0" \
847 "bdev=sda3\0"
852 "setenv ramdiskaddr 0x02000000;" \
853 "setenv fdtaddr 0x00c00000;" \
854 "setenv loadaddr 0x1000000;" \