Lines Matching +full:0 +full:xfdd00000
32 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
45 #define CONFIG_SYS_TEXT_BASE 0xeff40000
49 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
75 #define CONFIG_ENV_SPI_BUS 0
76 #define CONFIG_ENV_SPI_CS 0
78 #define CONFIG_ENV_SPI_MODE 0
79 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
80 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
81 #define CONFIG_ENV_SECT_SIZE 0x10000
84 #define CONFIG_SYS_MMC_ENV_DEV 0
85 #define CONFIG_ENV_SIZE 0x2000
93 #define CONFIG_ENV_SIZE 0x2000
94 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
97 #define CONFIG_ENV_SIZE 0x2000
98 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
119 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
127 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
128 #define CONFIG_SYS_MEMTEST_END 0x00400000
134 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
136 #define CONFIG_SYS_DCSRBAR 0xf0000000
137 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
142 #define CONFIG_SYS_EEPROM_BUS_NUM 0
143 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
152 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
161 #define CONFIG_SYS_SPD_BUS_NUM 0
162 #define SPD_EEPROM_ADDRESS 0x51
169 #define CONFIG_SYS_FLASH_BASE 0xe0000000
170 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
172 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
174 + 0x8000000) | \
178 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
188 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
192 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
193 FTIM0_NOR_TEADC(0x5) | \
194 FTIM0_NOR_TEAHC(0x5))
195 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
196 FTIM1_NOR_TRAD_NOR(0x1A) |\
197 FTIM1_NOR_TSEQRAD_NOR(0x13))
198 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
199 FTIM2_NOR_TCH(0x4) | \
200 FTIM2_NOR_TWPH(0x0E) | \
201 FTIM2_NOR_TWP(0x1c))
202 #define CONFIG_SYS_NOR_FTIM3 0x0
214 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
216 #define QIXIS_BASE 0xffdf0000
217 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
218 #define QIXIS_LBMAP_SWITCH 0x06
219 #define QIXIS_LBMAP_MASK 0x0f
220 #define QIXIS_LBMAP_SHIFT 0
221 #define QIXIS_LBMAP_DFLTBANK 0x00
222 #define QIXIS_LBMAP_ALTBANK 0x04
223 #define QIXIS_RST_CTL_RESET 0x31
224 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
225 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
226 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
227 #define QIXIS_RST_FORCE_MEM 0x01
229 #define CONFIG_SYS_CSPR3_EXT (0xf)
235 #define CONFIG_SYS_CSOR3 0x0
237 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
238 FTIM0_GPCM_TEADC(0x0e) | \
239 FTIM0_GPCM_TEAHC(0x0e))
240 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
241 FTIM1_GPCM_TRAD(0x3f))
242 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
243 FTIM2_GPCM_TCH(0x8) | \
244 FTIM2_GPCM_TWP(0x1f))
245 #define CONFIG_SYS_CS3_FTIM3 0x0
248 #define CONFIG_SYS_NAND_BASE 0xff800000
249 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
251 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
269 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
270 FTIM0_NAND_TWP(0x18) | \
271 FTIM0_NAND_TWCHT(0x07) | \
272 FTIM0_NAND_TWH(0x0a))
273 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
274 FTIM1_NAND_TWBE(0x39) | \
275 FTIM1_NAND_TRR(0x0e) | \
276 FTIM1_NAND_TRP(0x18))
277 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
278 FTIM2_NAND_TREH(0x0a) | \
279 FTIM2_NAND_TWHRE(0x1e))
280 #define CONFIG_SYS_NAND_FTIM3 0x0
354 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
355 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
356 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
361 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
377 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
382 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
383 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
384 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
385 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
391 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
409 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
410 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
411 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
412 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
413 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
414 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
415 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
416 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
418 #define I2C_MUX_PCA_ADDR 0x77
419 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
422 #define I2C_MUX_CH_DEFAULT 0x8
423 #define I2C_MUX_CH_DIU 0xC
426 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
427 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
434 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
440 #define CONFIG_SF_DEFAULT_MODE 0
444 * Memory space is mapped 1-1, but I/O space must start from 0.
450 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
451 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
452 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
453 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
454 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
455 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
456 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
457 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
462 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
463 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
464 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
465 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
466 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
467 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
468 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
469 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
474 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
475 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
476 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
477 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
478 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
479 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
480 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
481 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
486 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
487 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
488 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
489 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
490 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
491 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
492 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
493 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
539 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
540 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
541 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
542 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
543 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
549 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
551 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
552 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
553 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
554 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
555 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
561 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
571 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
572 * env, so we got 0x110000.
575 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
578 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
580 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
589 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
590 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
592 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
593 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
602 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
603 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
604 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
605 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
609 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01
610 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02
612 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
613 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
614 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
615 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
623 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14
624 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18
632 "spi0=spife110000.0"
636 "128k(dtb),96m(fs),-(user);spife110000.0:" \
652 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
680 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
681 "netdev=eth0\0" \
682 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
683 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
684 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
690 "cmp.b $loadaddr $ubootaddr $filesize\0" \
691 "consoledev=ttyS0\0" \
692 "ramdiskaddr=2000000\0" \
693 "ramdiskfile=t1040qds/ramdisk.uboot\0" \
694 "fdtaddr=1e00000\0" \
695 "fdtfile=t1040qds/t1040qds.dtb\0" \
696 "bdev=sda3\0"
701 "setenv ramdiskaddr 0x02000000;" \
702 "setenv fdtaddr 0x00c00000;" \
703 "setenv loadaddr 0x1000000;" \