Lines Matching +full:0 +full:x00200000
35 #define CONFIG_SYS_TEXT_BASE 0x00201000
36 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
37 #define CONFIG_SPL_PAD_TO 0x40000
38 #define CONFIG_SPL_MAX_SIZE 0x28000
39 #define RESET_VECTOR_OFFSET 0x27FFC
40 #define BOOT_PAGE_OFFSET 0x27000
49 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
50 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
58 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
73 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
76 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
77 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
90 #define CONFIG_SYS_TEXT_BASE 0xeff40000
94 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
109 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
110 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
112 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
113 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
115 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
116 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
123 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
124 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
126 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
127 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
129 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
131 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
132 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
136 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
138 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
140 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
142 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
143 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
148 #define CONFIG_ENV_SPI_BUS 0
149 #define CONFIG_ENV_SPI_CS 0
151 #define CONFIG_ENV_SPI_MODE 0
152 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
153 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
154 #define CONFIG_ENV_SECT_SIZE 0x10000
157 #define CONFIG_SYS_MMC_ENV_DEV 0
158 #define CONFIG_ENV_SIZE 0x2000
159 #define CONFIG_ENV_OFFSET (512 * 0x800)
162 #define CONFIG_ENV_SIZE 0x2000
165 #define CONFIG_ENV_ADDR 0xffe20000
166 #define CONFIG_ENV_SIZE 0x2000
168 #define CONFIG_ENV_SIZE 0x2000
171 #define CONFIG_ENV_SIZE 0x2000
172 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
193 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
196 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
197 #define CONFIG_SYS_MEMTEST_END 0x00400000
203 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
215 #define CONFIG_SYS_DCSRBAR 0xf0000000
216 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
222 #define CONFIG_SYS_EEPROM_BUS_NUM 0
223 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
232 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
238 #define CONFIG_SYS_SPD_BUS_NUM 0
239 #define SPD_EEPROM_ADDRESS 0x51
246 #define CONFIG_SYS_FLASH_BASE 0xe0000000
248 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
253 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
255 + 0x8000000) | \
259 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
267 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
268 FTIM0_NOR_TEADC(0x5) | \
269 FTIM0_NOR_TEAHC(0x5))
270 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
271 FTIM1_NOR_TRAD_NOR(0x1A) |\
272 FTIM1_NOR_TSEQRAD_NOR(0x13))
273 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
274 FTIM2_NOR_TCH(0x4) | \
275 FTIM2_NOR_TWPH(0x0E) | \
276 FTIM2_NOR_TWP(0x1c))
277 #define CONFIG_SYS_NOR_FTIM3 0x0
289 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
291 #define QIXIS_BASE 0xffdf0000
293 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
297 #define QIXIS_LBMAP_SWITCH 0x06
298 #define QIXIS_LBMAP_MASK 0x0f
299 #define QIXIS_LBMAP_SHIFT 0
300 #define QIXIS_LBMAP_DFLTBANK 0x00
301 #define QIXIS_LBMAP_ALTBANK 0x04
302 #define QIXIS_RST_CTL_RESET 0x31
303 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
304 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
305 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
306 #define QIXIS_RST_FORCE_MEM 0x01
308 #define CONFIG_SYS_CSPR3_EXT (0xf)
314 #define CONFIG_SYS_CSOR3 0x0
316 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
317 FTIM0_GPCM_TEADC(0x0e) | \
318 FTIM0_GPCM_TEAHC(0x0e))
319 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
320 FTIM1_GPCM_TRAD(0x3f))
321 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
322 FTIM2_GPCM_TCH(0x8) | \
323 FTIM2_GPCM_TWP(0x1f))
324 #define CONFIG_SYS_CS3_FTIM3 0x0
327 #define CONFIG_SYS_NAND_BASE 0xff800000
329 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
333 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
351 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
352 FTIM0_NAND_TWP(0x18) | \
353 FTIM0_NAND_TWCHT(0x07) | \
354 FTIM0_NAND_TWH(0x0a))
355 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
356 FTIM1_NAND_TWBE(0x39) | \
357 FTIM1_NAND_TRR(0x0e) | \
358 FTIM1_NAND_TRP(0x18))
359 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
360 FTIM2_NAND_TREH(0x0a) | \
361 FTIM2_NAND_TWHRE(0x1e))
362 #define CONFIG_SYS_NAND_FTIM3 0x0
440 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
442 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
443 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
449 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
450 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
453 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
466 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
471 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
472 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
473 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
474 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
481 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
497 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
499 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
500 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
501 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
503 #define I2C_MUX_PCA_ADDR 0x77
504 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
505 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
506 #define I2C_RETIMER_ADDR 0x18
509 #define I2C_MUX_CH_DEFAULT 0x8
510 #define I2C_MUX_CH_DIU 0xC
511 #define I2C_MUX_CH5 0xD
512 #define I2C_MUX_CH7 0xF
515 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
516 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
523 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
532 #define CONFIG_SF_DEFAULT_MODE 0
536 * Memory space is mapped 1-1, but I/O space must start from 0.
548 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
550 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
551 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
553 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
554 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
556 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
557 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
558 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
560 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
562 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
564 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
569 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
571 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
572 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
574 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
575 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
577 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
578 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
579 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
581 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
583 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
585 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
590 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
592 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
593 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
595 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
596 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
598 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
599 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
600 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
602 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
604 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
606 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
648 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
650 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
654 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
655 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
656 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
662 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
664 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
666 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
670 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
671 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
672 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
678 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
687 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
688 * env, so we got 0x110000.
691 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
692 #define CONFIG_SYS_QE_FW_ADDR 0x130000
695 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
697 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
700 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
701 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
715 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
718 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
719 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
721 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
722 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
731 #define RGMII_PHY1_ADDR 0x1
732 #define RGMII_PHY2_ADDR 0x2
733 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
734 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
735 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
736 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
737 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
738 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
739 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
753 "spi0=spife110000.0"
757 "128k(dtb),96m(fs),-(user);spife110000.0:" \
773 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
797 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \
798 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
799 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
800 "ramdiskfile=t1024qds/ramdisk.uboot\0" \
801 "fdtfile=t1024qds/t1024qds.dtb\0" \
802 "netdev=eth0\0" \
803 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
804 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
805 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
811 "cmp.b $loadaddr $ubootaddr $filesize\0" \
812 "consoledev=ttyS0\0" \
813 "ramdiskaddr=2000000\0" \
814 "fdtaddr=d00000\0" \
815 "bdev=sda3\0"
820 "setenv ramdiskaddr 0x02000000;" \
821 "setenv fdtaddr 0x00c00000;" \
822 "setenv loadaddr 0x1000000;" \