Lines Matching +full:0 +full:x8000c000
43 #define CONFIG_SYS_TEXT_BASE 0xfff80000
58 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
59 #define CONFIG_SYS_MEMTEST_END 0x00400000
64 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
69 #define CONFIG_SYS_CCSRBAR 0xe0000000
82 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
84 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
92 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
96 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
97 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
98 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
99 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
100 #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644
101 #define CONFIG_SYS_DDR_TIMING_2 0x002888D0
102 #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000
103 #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040
104 #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521
105 #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000
106 #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000
107 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
108 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000
109 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
110 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
111 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
112 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604
113 #define CONFIG_SYS_DDR_CDR_1 0x80040000
114 #define CONFIG_SYS_DDR_CDR_2 0x00000000
115 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
116 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
117 #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */
118 #define CONFIG_SYS_DDR_CONTROL2 0x24400000
120 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
121 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
122 #define CONFIG_SYS_DDR_SBE 0x00010000
130 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
133 #define CONFIG_SYS_BCSR_BASE 0xf8000000
136 /*Chip select 0 - Flash*/
137 #define CONFIG_FLASH_BR_PRELIM 0xfe000801
138 #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7
141 #define CONFIG_SYS_BR1_PRELIM 0xf8000801
142 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
145 #define CONFIG_SYS_BR4_PRELIM 0xf8008801
146 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
149 #define CONFIG_SYS_BR5_PRELIM 0xf8010801
150 #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7
166 #define CONFIG_SYS_NAND_BASE 0xFC000000
168 #define CONFIG_SYS_NAND_BASE 0xFFF00000
172 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
173 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
177 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
178 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
179 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
191 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
204 #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
205 #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */
206 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
207 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
210 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
211 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
224 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
232 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
233 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
241 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
243 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
244 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
245 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
246 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
255 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
259 #define PLPPAR1_I2C_BIT_MASK 0x0000000F
260 #define PLPPAR1_I2C2_VAL 0x00000000
261 #define PLPPAR1_ESDHC_VAL 0x0000000A
262 #define PLPDIR1_I2C_BIT_MASK 0x0000000F
263 #define PLPDIR1_I2C2_VAL 0x0000000F
264 #define PLPDIR1_ESDHC_VAL 0x00000006
265 #define PLPPAR1_UART0_BIT_MASK 0x00000fc0
266 #define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80
267 #define PLPDIR1_UART0_BIT_MASK 0x00000fc0
268 #define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80
272 * Memory Addresses are mapped 1-1. I/O is mapped from 0
275 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
276 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
277 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
278 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
279 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
280 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
281 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
282 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
284 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
285 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
287 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
296 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
305 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
316 #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */
337 #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */
358 #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */
379 #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */
427 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
428 #define CONFIG_ENV_SIZE 0x2000
436 #define CONFIG_SYS_QE_FW_ADDR 0xfff00000
460 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
496 "netdev=eth0\0" \
497 "consoledev=ttyS0\0" \
498 "ramdiskaddr=600000\0" \
499 "ramdiskfile=your.ramdisk.u-boot\0" \
500 "fdtaddr=400000\0" \
501 "fdtfile=your.fdt.dtb\0" \
505 "console=$consoledev,$baudrate $othbootargs\0" \
507 "console=$consoledev,$baudrate $othbootargs\0" \