Lines Matching +full:bit +full:- +full:banged
6 * SPDX-License-Identifier: GPL-2.0+
26 * assume U-Boot is less than 0.5MB
31 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
87 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
90 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
102 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
135 * port-size = 32-bits = BR2[19:20] = 11
155 * 9 columns OR2[19-21] = 010
156 * 13 rows OR2[23-25] = 100
190 * 32KB, 8-bit wide for ADS config reg
200 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
232 * Memory space is mapped 1-1, but I/O space must start from 0.
250 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
274 /* Options are: TSEC[0-1] */
286 * - Rx-CLK is CLK13
287 * - Tx-CLK is CLK14
288 * - Select bus for bd/buffers
289 * - Full duplex
305 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
308 * GPIO pins used for bit-banged MII communications
315 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
316 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
317 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
319 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ argument
320 else iop->pdat &= ~0x00400000
322 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ argument
323 else iop->pdat &= ~0x00200000
337 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
358 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
402 "ramdiskfile=your.ramdisk.u-boot\0" \
413 "bootm $loadaddr - $fdtaddr"