Lines Matching +full:0 +full:x98000000
18 #define CONFIG_SYS_TEXT_BASE 0xf8f40000
19 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
24 #define CONFIG_SYS_TEXT_BASE 0xf8f40000
25 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
29 #define CONFIG_SYS_TEXT_BASE 0xeff40000
33 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
70 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */
71 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */
76 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
78 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
85 #define CONFIG_SYS_CCSRBAR 0xffe00000
99 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
101 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
108 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
113 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
114 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
115 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
116 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
117 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
118 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
119 #define CONFIG_SYS_DDR_MODE_1 0x00480432
120 #define CONFIG_SYS_DDR_MODE_2 0x00000000
121 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
122 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
123 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
124 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
125 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
126 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
127 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
129 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
130 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
131 #define CONFIG_SYS_DDR_SBE 0x00010000
143 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
144 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
145 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
146 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
149 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
152 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable
153 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
154 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
155 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
156 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
157 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
163 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
165 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
171 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
172 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
177 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
179 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
206 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
208 #define PIXIS_BASE_PHYS 0xfffdf0000ull
214 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
216 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
217 #define PIXIS_VER 0x1 /* Board version at offset 1 */
218 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
219 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */
220 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
221 #define PIXIS_PWR 0x5 /* PIXIS Power status register */
222 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */
223 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
224 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
225 #define PIXIS_VCTL 0x10 /* VELA Control Register */
226 #define PIXIS_VSTAT 0x11 /* VELA Status Register */
227 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
228 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
229 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
230 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
231 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */
232 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
233 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */
234 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */
235 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */
236 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */
237 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */
238 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
239 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
240 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
241 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */
242 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */
243 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */
244 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */
245 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */
246 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */
247 #define PIXIS_VWATCH 0x24 /* Watchdog Register */
248 #define PIXIS_LED 0x25 /* LED Register */
250 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */
253 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
254 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
255 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e
258 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
259 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
269 #define CONFIG_SYS_NAND_BASE 0xffa00000
271 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
276 #define CONFIG_SYS_NAND_BASE 0xfff00000
278 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
284 CONFIG_SYS_NAND_BASE + 0x40000, \
285 CONFIG_SYS_NAND_BASE + 0x80000, \
286 CONFIG_SYS_NAND_BASE + 0xC0000}
292 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
293 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
297 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
298 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
299 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
308 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
323 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
330 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
338 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
352 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
360 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
361 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
369 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
370 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
372 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
373 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
374 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
383 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
394 #define CONFIG_SF_DEFAULT_MODE 0
399 * Memory space is mapped 1-1, but I/O space must start from 0.
402 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
404 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000
405 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
407 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
408 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
410 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
411 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
412 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
414 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull
416 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
418 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
422 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
424 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000
425 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull
427 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
428 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
430 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */
431 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
432 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
434 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull
436 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
438 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
442 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
444 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000
445 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull
447 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
448 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
450 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */
451 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
452 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
454 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull
456 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
458 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
462 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
464 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
465 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
467 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
468 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
470 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
471 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
472 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
474 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull
476 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
478 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
502 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
535 #define SGMII_RISER_PHY_OFFSET 0x1c
538 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */
543 #define TSEC1_PHYIDX 0
544 #define TSEC3_PHYIDX 0
556 #define CONFIG_ENV_SPI_BUS 0
557 #define CONFIG_ENV_SPI_CS 0
559 #define CONFIG_ENV_SPI_MODE 0
560 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
561 #define CONFIG_ENV_OFFSET 0xF0000
562 #define CONFIG_ENV_SECT_SIZE 0x10000
565 #define CONFIG_ENV_SIZE 0x2000
566 #define CONFIG_SYS_MMC_ENV_DEV 0
568 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
569 #define CONFIG_ENV_SIZE 0x2000
573 #define CONFIG_ENV_SIZE 0x2000
574 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
604 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
645 "netdev=eth0\0" \
646 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
657 " $filesize\0" \
658 "consoledev=ttyS0\0" \
659 "ramdiskaddr=2000000\0" \
660 "ramdiskfile=8536ds/ramdisk.uboot\0" \
661 "fdtaddr=1e00000\0" \
662 "fdtfile=8536ds/mpc8536ds.dtb\0" \
663 "bdev=sda3\0" \
664 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"