Lines Matching +full:0 +full:x43000000
19 #define CONFIG_SYS_TEXT_BASE 0xFE000000
88 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
89 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
92 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */
95 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
96 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
97 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
102 #define CONFIG_SYS_SICRH 0x08200000
103 #define CONFIG_SYS_SICRL 0x00000000
108 #define CONFIG_SYS_OBIR 0x30100000
113 #define CONFIG_SYS_IMMR 0xE0000000
126 #define CONFIG_VSC7385_IMAGE 0xFE7FE000
134 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
137 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
151 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
157 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
158 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
159 | (0 << TIMING_CFG0_WRT_SHIFT) \
160 | (0 << TIMING_CFG0_RRT_SHIFT) \
161 | (0 << TIMING_CFG0_WWT_SHIFT) \
166 /* 0x00260802 */ /* DDR400 */
175 /* 0x3937d322 */
176 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
183 /* 0x02984cc8 */
186 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
187 /* 0x06090100 */
194 /* 0x43088000 */
198 /* 0x43000000 */
200 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
201 #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
202 | (0x0442 << SDRAM_MODE_SD_SHIFT))
203 /* 0x04400442 */ /* DDR400 */
204 #define CONFIG_SYS_DDR_MODE2 0x00000000
210 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
211 #define CONFIG_SYS_MEMTEST_END 0x0ef70010
231 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
232 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
241 #define CONFIG_SYS_LBC_LBCR 0x00000000
249 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
258 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
269 /* 0xFF800191 */
281 #define CONFIG_SYS_NAND_BASE 0xE0600000
299 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
307 /* 0xF0000801 */
316 /* 0xfffe09ff */
330 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
335 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
336 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
340 #define CONFIG_FSL_SERDES1 0xe3000
341 #define CONFIG_FSL_SERDES2 0xe3100
347 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
348 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
349 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
355 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
361 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
363 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
364 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
366 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
367 #define CONFIG_SYS_PCI_IO_BASE 0x00000000
368 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
369 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
372 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
373 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
375 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
376 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
377 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
378 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
379 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
380 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
381 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
382 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
383 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
385 #define CONFIG_SYS_PCIE2_BASE 0xC0000000
386 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
387 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
388 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
389 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
390 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
391 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
392 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
393 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
399 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
414 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
417 #define TSEC1_PHYIDX 0
423 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
424 #define TSEC2_PHY_ADDR 0x1c
426 #define TSEC2_PHYIDX 0
429 /* Options are: TSEC[0-1] */
442 #define CONFIG_SYS_SATA1_OFFSET 0x18000
446 #define CONFIG_SYS_SATA2_OFFSET 0x19000
460 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */
461 #define CONFIG_ENV_SIZE 0x4000
463 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000)
464 #define CONFIG_ENV_SIZE 0x2000
497 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
510 #define CONFIG_SYS_HID0_INIT 0x000000000
523 #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
615 #define CONFIG_SYS_IBAT6L (0)
616 #define CONFIG_SYS_IBAT6U (0)
617 #define CONFIG_SYS_IBAT7L (0)
618 #define CONFIG_SYS_IBAT7U (0)
652 "netdev=" CONFIG_NETDEV "\0" \
653 "uboot=" CONFIG_UBOOTPATH "\0" \
664 " $filesize\0" \
665 "fdtaddr=780000\0" \
666 "fdtfile=" CONFIG_FDTFILE "\0" \
667 "ramdiskaddr=1000000\0" \
668 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
669 "console=ttyS0\0" \
671 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
675 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"