Lines Matching +full:0 +full:x43000000
18 #define CONFIG_SYS_TEXT_BASE 0xFE000000
87 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */
92 #define CONFIG_SYS_SICRH 0x00000000
93 #define CONFIG_SYS_SICRL 0x00000000
98 #define CONFIG_SYS_OBIR 0x31100000
106 #define CONFIG_SYS_IMMR 0xE0000000
111 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
119 /* 0x80080001 */ /* ODT 150ohm on SoC */
128 #define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */
136 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
142 /* 0x80010202 */
143 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
144 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
145 | (0 << TIMING_CFG0_WRT_SHIFT) \
146 | (0 << TIMING_CFG0_RRT_SHIFT) \
147 | (0 << TIMING_CFG0_WWT_SHIFT) \
152 /* 0x00620802 */
161 /* 0x3935d322 */
169 /* 0x131088c8 */
170 #define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
171 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
172 /* 0x03E00100 */
173 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
174 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
175 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
176 | (0x1432 << SDRAM_MODE_SD_SHIFT))
178 #define CONFIG_SYS_DDR_MODE2 0x00000000
185 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
186 #define CONFIG_SYS_MEMTEST_END 0x00140000
207 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
208 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
217 #define CONFIG_SYS_LBC_LBCR 0x00000000
225 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
246 /* 0xFE000FF7 */
258 #define CONFIG_SYS_BCSR 0xF8000000
267 /* 0xF8000801 */
276 /* 0xFFFFE9F7 */
284 #define CONFIG_SYS_NAND_BASE 0xE0600000
298 /* 0xFFFF919E */
309 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
314 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
315 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
321 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
322 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
323 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
329 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
335 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
337 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
338 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
340 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
341 #define CONFIG_SYS_PCI_IO_BASE 0x00000000
342 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
343 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
346 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
347 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
349 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
350 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
351 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
352 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
353 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
354 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
355 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
356 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
357 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
359 #define CONFIG_SYS_PCIE2_BASE 0xC0000000
360 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
361 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
362 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
363 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
364 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
365 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
366 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
367 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
383 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
390 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
392 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
407 #define TSEC1_PHYIDX 0
408 #define TSEC2_PHYIDX 0
412 /* Options are: TSEC[0-1] */
417 #define CONFIG_FSL_SERDES1 0xe3000
418 #define CONFIG_FSL_SERDES2 0xe3100
428 #define CONFIG_SYS_SATA1_OFFSET 0x18000
432 #define CONFIG_SYS_SATA2_OFFSET 0x19000
446 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
447 #define CONFIG_ENV_SIZE 0x2000
449 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
450 #define CONFIG_ENV_SIZE 0x2000
483 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
496 #define CONFIG_SYS_HID0_INIT 0x000000000
508 #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
600 #define CONFIG_SYS_IBAT6L (0)
601 #define CONFIG_SYS_IBAT6U (0)
602 #define CONFIG_SYS_IBAT7L (0)
603 #define CONFIG_SYS_IBAT7U (0)
628 "netdev=eth0\0" \
629 "consoledev=ttyS0\0" \
630 "ramdiskaddr=1000000\0" \
631 "ramdiskfile=ramfs.83xx\0" \
632 "fdtaddr=780000\0" \
633 "fdtfile=mpc8379_mds.dtb\0" \