include/configs/MPC8349EMDS.h

2  * (C) Copyright 2006-2010
5  * SPDX-License-Identifier:	GPL-2.0+
73  * 32-bit data path mode.
75  * Please note that using this mode for devices with the real density of 64-bit
79  * 128MB); normally this define should be used for devices with real 32-bit
92  * DDRCDR - DDR Control Driver Register
125 #define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
130 /* set burst length to 8 for 32-bit data path */
134 /* the default burst length is 4 - for 64-bit data path */
191  * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
215 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
245  *    port-size = 32-bits = BR2[19:20] = 11
255 					| BR_PS_32	/* 32-bit port */ \
268  *    9 columns OR2[19-21] = 010
269  *    13 rows   OR2[23-25] = 100
278 			| ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
279 			| ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
336 #undef CONFIG_SOFT_SPI			/* SPI bit-banged */
338 /* GPIOs.  Used as SPI chip selects */
354  * Addresses are mapped 1-1.
393 	#define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
420 /* Options are: TSEC[0-1] */
426  * Configure on-board RTC
445 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
449 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
566 #define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
567 #define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count (0-7) */
568 #define CONFIG_SYS_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
569 #define CONFIG_SYS_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */
570 #define CONFIG_SYS_SCCR_TSEC1CM	1	/* TSEC1 clock mode (0-3) */
571 #define CONFIG_SYS_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */
706 #define CONFIG_PREBOOT	"echo;"	\
707 	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
708 	"echo"
726 	"load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"		\
742 	"bootm $loadaddr - $fdtaddr"