Lines Matching +full:0 +full:xf0000000
24 #define CONFIG_SYS_TEXT_BASE 0xFE000000
47 #define CONFIG_SYS_IMMR 0xE0000000
50 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
51 #define CONFIG_SYS_MEMTEST_END 0x00100000
64 #define CONFIG_SYS_SPD_BUS_NUM 0
65 #define SPD_EEPROM_ADDRESS1 0x52
66 #define SPD_EEPROM_ADDRESS2 0x51
70 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
84 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
94 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
100 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
107 #define CONFIG_SYS_DDRCDR 0x80080001
108 #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
109 #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
110 #define CONFIG_SYS_DDR_TIMING_0 0x00220802
111 #define CONFIG_SYS_DDR_TIMING_1 0x38357322
112 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
113 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
114 #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
115 #define CONFIG_SYS_DDR_MODE 0x47d00432
116 #define CONFIG_SYS_DDR_MODE2 0x8000c000
117 #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
118 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
119 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
124 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
125 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
126 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
127 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
132 #define CONFIG_SYS_DDR_MODE 0x00000023
136 #define CONFIG_SYS_DDR_MODE 0x00000022
144 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
152 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
193 #define CONFIG_SYS_BCSR 0xE2400000
201 /* 0x00000801 */
208 /* 0xFFFFE8F0 */
211 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
212 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
229 #define CONFIG_SYS_LBC_LBCR 0x00000000
241 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
244 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
250 * 0 4 8 12 16 20 24 28
258 /* 0xF0001861 */
266 * 64MB mask for AM, OR2[0:7] = 1111 1100
272 * 0 4 8 12 16 20 24 28
281 /* 0xFC006901 */
284 #define CONFIG_SYS_LBC_LSRT 0x32000000
286 #define CONFIG_SYS_LBC_MRTPR 0x20000000
313 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
318 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
319 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
328 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
329 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
331 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
332 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
333 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
340 #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
341 #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
344 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
346 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
356 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
358 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
359 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
361 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
362 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
363 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
364 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
366 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
368 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
369 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
371 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
372 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
373 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
374 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
391 #define PCI_ENET0_IOADDR 0xFIXME
392 #define PCI_ENET0_MEMADDR 0xFIXME
393 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
397 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
413 #define TSEC1_PHY_ADDR 0
415 #define TSEC1_PHYIDX 0
416 #define TSEC2_PHYIDX 0
420 /* Options are: TSEC[0-1] */
429 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
437 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
438 #define CONFIG_ENV_SIZE 0x2000
445 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
446 #define CONFIG_ENV_SIZE 0x2000
470 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
481 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
490 #elif 0 /*396/132*/
497 #elif 0 /*264/132*/
504 #elif 0 /*132/132*/
511 #elif 0 /*264/264 */
566 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
567 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
568 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
569 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
570 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
571 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
574 #define CONFIG_SYS_SICRH 0
577 #define CONFIG_SYS_HID0_INIT 0x000000000
589 /* DDR @ 0x00000000 */
598 /* PCI @ 0x80000000 */
617 #define CONFIG_SYS_IBAT1L (0)
618 #define CONFIG_SYS_IBAT1U (0)
619 #define CONFIG_SYS_IBAT2L (0)
620 #define CONFIG_SYS_IBAT2U (0)
640 #define CONFIG_SYS_IBAT3L (0)
641 #define CONFIG_SYS_IBAT3U (0)
642 #define CONFIG_SYS_IBAT4L (0)
643 #define CONFIG_SYS_IBAT4U (0)
646 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
656 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
657 #define CONFIG_SYS_IBAT6L (0xF0000000 \
661 #define CONFIG_SYS_IBAT6U (0xF0000000 \
666 #define CONFIG_SYS_IBAT7L (0)
667 #define CONFIG_SYS_IBAT7U (0)
711 "netdev=eth0\0" \
712 "hostname=mpc8349emds\0" \
714 "nfsroot=${serverip}:${rootpath}\0" \
715 "ramargs=setenv bootargs root=/dev/ram rw\0" \
718 ":${hostname}:${netdev}:off panic=1\0" \
719 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
721 "bootm ${kernel_addr}\0" \
723 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
725 "bootm\0" \
726 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
728 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
729 "upd=run load update\0" \
730 "fdtaddr=780000\0" \
731 "fdtfile=mpc834x_mds.dtb\0" \