Lines Matching +full:0 +full:x8000c000
18 #define CONFIG_SYS_TEXT_BASE 0xFE000000
73 #define CONFIG_SYS_SICRL 0x00000000
80 #define CONFIG_SYS_IMMR 0xE0000000
85 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
88 #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
94 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
104 /* 0x80840102 */
105 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
106 | (0 << TIMING_CFG0_WRT_SHIFT) \
107 | (0 << TIMING_CFG0_RRT_SHIFT) \
108 | (0 << TIMING_CFG0_WWT_SHIFT) \
113 /* 0x00220802 */
122 /* 0x3935D322 */
123 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
130 /* 0x0F9048CA */
131 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
133 /* 0x02000000 */
134 #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
135 | (0x0232 << SDRAM_MODE_SD_SHIFT))
136 /* 0x44400232 */
137 #define CONFIG_SYS_DDR_MODE2 0x8000c000
140 /* 0x03200064 */
141 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
145 /* 0x43080000 */
146 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
153 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
154 #define CONFIG_SYS_MEMTEST_END 0x00100000
175 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */
176 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
185 #define CONFIG_SYS_LBC_LBCR 0x00000000
192 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
213 /* 0xfe006ff7 */
223 #define CONFIG_SYS_BCSR 0xF8000000
240 /* 0xFFFFE9F7 */
245 /* PIB window base 0xF8008000 */
246 #define CONFIG_SYS_PIB_BASE 0xF8008000
258 /* 0xF8008801 */
267 /* 0xffffe9f7 */
277 /* 0xF8010801 */
286 /* 0xffffe9f7 */
294 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
299 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
300 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
309 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
310 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
311 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
317 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
323 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
325 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
326 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
328 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
329 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
330 #define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
331 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
334 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
335 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
344 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
384 #define CONFIG_ENV_SECT_SIZE 0x20000
385 #define CONFIG_ENV_SIZE 0x2000
387 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
388 #define CONFIG_ENV_SIZE 0x2000
412 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
426 #define CONFIG_SYS_HID0_INIT 0x000000000
486 #define CONFIG_SYS_IBAT4L (0)
487 #define CONFIG_SYS_IBAT4U (0)
523 #define CONFIG_SYS_IBAT6L (0)
524 #define CONFIG_SYS_IBAT6U (0)
525 #define CONFIG_SYS_IBAT7L (0)
526 #define CONFIG_SYS_IBAT7U (0)
549 "netdev=eth0\0" \
550 "consoledev=ttyS0\0" \
551 "ramdiskaddr=1000000\0" \
552 "ramdiskfile=ramfs.83xx\0" \
553 "fdtaddr=780000\0" \
554 "fdtfile=mpc832x_mds.dtb\0" \