include/configs/MPC8323ERDB.h

19 #define	CONFIG_SYS_TEXT_BASE	0xFE000000
57 #define CONFIG_SYS_SICRL		0x00000000
62 #define CONFIG_SYS_IMMR		0xE0000000
67 #define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
68 #define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count (0-7) */
69 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
75 #define CONFIG_SYS_DDR_BASE	0x00000000	/* DDR is system memory */
83 #define SPD_EEPROM_ADDRESS	0x51	/* DDR SODIMM */
91 				/* 0x80010101 */
92 #define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
93 				| (0 << TIMING_CFG0_WRT_SHIFT) \
94 				| (0 << TIMING_CFG0_RRT_SHIFT) \
95 				| (0 << TIMING_CFG0_WWT_SHIFT) \
100 				/* 0x00220802 */
109 				/* 0x26253222 */
117 				/* 0x1f9048c7 */
118 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
120 				/* 0x02000000 */
121 #define CONFIG_SYS_DDR_MODE	((0x4448 << SDRAM_MODE_ESD_SHIFT) \
122 				| (0x0232 << SDRAM_MODE_SD_SHIFT))
123 				/* 0x44480232 */
124 #define CONFIG_SYS_DDR_MODE2	0x8000c000
127 				/* 0x03200064 */
128 #define CONFIG_SYS_DDR_CS0_BNDS	0x00000003
132 				/* 0x43080000 */
133 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
140 #define CONFIG_SYS_MEMTEST_START	0x00030000	/* memtest region */
141 #define CONFIG_SYS_MEMTEST_END		0x03f00000
162 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
163 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
172 #define CONFIG_SYS_LBC_LBCR		0x00000000
179 #define CONFIG_SYS_FLASH_BASE	0xFE000000	/* FLASH base address */
200 				/* 0xFE006FF7 */
213 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
218 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
219 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
228 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
229 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
230 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
235 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
244 #define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
246 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
247 #define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
249 #define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
250 #define CONFIG_SYS_PCI1_IO_BASE		0xd0000000
252 #define CONFIG_SYS_PCI1_IO_SIZE		0x04000000	/* 64M */
260 #define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */
289 #define CONFIG_SYS_UEC2_PHY_ADDR	0
300 	#define CONFIG_ENV_SECT_SIZE	0x20000
301 	#define CONFIG_ENV_SIZE		0x2000
303 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
304 	#define CONFIG_ENV_SIZE		0x2000
328 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
342 #define CONFIG_SYS_HID0_INIT	0x000000000
389 #define CONFIG_SYS_IBAT3L	(0)
390 #define CONFIG_SYS_IBAT3U	(0)
426 #define CONFIG_SYS_IBAT5L	(0)
427 #define CONFIG_SYS_IBAT5U	(0)
428 #define CONFIG_SYS_IBAT6L	(0)
429 #define CONFIG_SYS_IBAT6U	(0)
437 #define CONFIG_SYS_IBAT7L	(0)
438 #define CONFIG_SYS_IBAT7U	(0)
457 #define CONFIG_SYS_I2C_MAC_OFFSET	0x7f00
473 	"netdev=" CONFIG_NETDEV "\0"					\
474 	"uboot=" CONFIG_UBOOTPATH "\0"					\
485 			" $filesize\0"	\
486 	"fdtaddr=780000\0"						\
487 	"fdtfile=" CONFIG_FDTFILE "\0"					\
488 	"ramdiskaddr=1000000\0"						\
489 	"ramdiskfile=" CONFIG_RAMDISKFILE "\0"				\
490 	"console=ttyS0\0"						\
492 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
496 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"