Lines Matching +full:0 +full:x8000c000
20 #define CONFIG_SYS_TEXT_BASE 0x11000000
21 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
27 #define CONFIG_SYS_TEXT_BASE 0x11000000
28 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
34 #define CONFIG_SYS_TEXT_BASE 0x11000000
35 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
44 #define CONFIG_SYS_TEXT_BASE 0x00201000
45 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000
47 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
48 #define CONFIG_SPL_RELOC_STACK 0x00100000
49 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
50 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
51 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
52 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
57 #define CONFIG_SYS_TEXT_BASE 0x8ff40000
61 #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc
82 * Memory space is mapped 1-1, but I/O space must start from 0.
86 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
87 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
88 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
89 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
90 #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000
91 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
92 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
93 #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000
118 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
119 #define CONFIG_SYS_MEMTEST_END 0x01ffffff
122 #define CONFIG_SYS_SPD_BUS_NUM 0
123 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */
124 #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */
127 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
130 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
137 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
138 #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302
139 #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302
140 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
141 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
142 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
143 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
144 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
145 #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F
147 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
148 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
149 #define CONFIG_SYS_DDR_RCW_1 0x00000000
150 #define CONFIG_SYS_DDR_RCW_2 0x00000000
151 #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000
152 #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050
153 #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001
154 #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400
156 #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008
157 #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010
158 #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001
159 #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400
161 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
162 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004
163 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846
164 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF
165 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
166 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520
167 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
168 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000
169 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608
171 #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000
172 #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104
173 #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45
174 #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114
175 #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000
176 #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50
177 #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000
178 #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513
179 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607
219 #define CONFIG_SYS_FLASH_BASE 0x88000000
224 #define CONFIG_SYS_NOR_CSPR 0x88000101
229 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \
230 | FTIM0_NOR_TEADC(0x03) \
231 | FTIM0_NOR_TAVDS(0x00) \
232 | FTIM0_NOR_TEAHC(0x0f))
233 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \
234 | FTIM1_NOR_TRAD_NOR(0x09) \
235 | FTIM1_NOR_TSEQRAD_NOR(0x09))
236 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \
237 | FTIM2_NOR_TCH(0x4) \
238 | FTIM2_NOR_TWPH(0x7) \
239 | FTIM2_NOR_TWP(0x1e))
240 #define CONFIG_SYS_NOR_FTIM3 0x0
258 #define CONFIG_SYS_NAND_BASE 0xff800000
276 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
277 | FTIM0_NAND_TWP(0x05) \
278 | FTIM0_NAND_TWCHT(0x02) \
279 | FTIM0_NAND_TWH(0x04))
280 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \
281 | FTIM1_NAND_TWBE(0x1e) \
282 | FTIM1_NAND_TRR(0x07) \
283 | FTIM1_NAND_TRP(0x05))
284 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
285 | FTIM2_NAND_TREH(0x04) \
286 | FTIM2_NAND_TWHRE(0x11))
287 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
301 #define CONFIG_SYS_FPGA_BASE 0xffb00000
302 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
305 #define QIXIS_LBMAP_MASK 0x07
306 #define QIXIS_LBMAP_SHIFT 0
307 #define QIXIS_LBMAP_DFLTBANK 0x00
308 #define QIXIS_LBMAP_ALTBANK 0x04
309 #define QIXIS_RST_CTL_RESET 0x83
310 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
311 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
312 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
321 #define CONFIG_SYS_CSOR2 0x0
323 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
324 FTIM0_GPCM_TEADC(0x0e) | \
325 FTIM0_GPCM_TEAHC(0x0e))
326 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
327 FTIM1_GPCM_TRAD(0x1f))
328 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
329 FTIM2_GPCM_TCH(0x8) | \
330 FTIM2_GPCM_TWP(0x1f))
331 #define CONFIG_SYS_CS2_FTIM3 0x0
370 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
371 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
385 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
393 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
394 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
395 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700)
396 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800)
401 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
403 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
404 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
405 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
412 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
414 #define CONFIG_SYS_EEPROM_BUS_NUM 0
423 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
426 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
447 #define TSEC1_PHY_ADDR 0
453 #define TSEC1_PHYIDX 0
454 #define TSEC2_PHYIDX 0
484 #define CONFIG_SYS_MMC_ENV_DEV 0
485 #define CONFIG_ENV_SIZE 0x2000
487 #define CONFIG_ENV_SPI_BUS 0
488 #define CONFIG_ENV_SPI_CS 0
490 #define CONFIG_ENV_SPI_MODE 0
491 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
492 #define CONFIG_ENV_SECT_SIZE 0x10000
493 #define CONFIG_ENV_SIZE 0x2000
499 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
500 #define CONFIG_ENV_SIZE 0x2000
503 #define CONFIG_ENV_SIZE 0x2000
504 #define CONFIG_ENV_SECT_SIZE 0x20000
516 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
555 #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
557 #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0"
561 "netdev=eth0\0" \
562 "uboot=" CONFIG_UBOOTPATH "\0" \
563 "loadaddr=1000000\0" \
564 "bootfile=uImage\0" \
565 "consoledev=ttyS0\0" \
566 "ramdiskaddr=2000000\0" \
567 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
568 "fdtaddr=1e00000\0" \
569 "fdtfile=bsc9132qds.dtb\0" \
570 "bdev=sda1\0" \
574 "isolcpus=0\0" \
578 "ext2load usb 0:4 $loadaddr $bootfile;" \
579 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
580 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
581 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
582 "debug_halt_off=mw ff7e0e30 0xf0000000;"
597 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
598 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \