Lines Matching +full:0 +full:xfdd00000
18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
22 #define CONFIG_SYS_TEXT_BASE 0x00201000
23 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
24 #define CONFIG_SPL_PAD_TO 0x40000
25 #define CONFIG_SPL_MAX_SIZE 0x28000
26 #define RESET_VECTOR_OFFSET 0x27FFC
27 #define BOOT_PAGE_OFFSET 0x27000
29 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
30 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
44 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
46 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
47 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
55 #define CONFIG_SYS_TEXT_BASE 0xeff40000
59 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
76 #define I2C_MUX_PCA_ADDR 0x77
80 #define I2C_CH_DEFAULT 0x8
81 #define I2C_CH_VSC3316 0xc
82 #define I2C_CH_VSC3308 0xd
84 #define VSC3316_TX_ADDRESS 0x70
85 #define VSC3316_RX_ADDRESS 0x71
86 #define VSC3308_TX_ADDRESS 0x02
87 #define VSC3308_RX_ADDRESS 0x03
91 #define I2C_CH_IDT 0x9
93 #define IDT_SERDES1_ADDRESS 0x6E
94 #define IDT_SERDES2_ADDRESS 0x6C
97 #define I2C_MUX_CH_VOL_MONITOR 0xa
98 #define I2C_VOL_MONITOR_ADDR 0x40
99 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
100 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
104 #define I2C_MUX_CH_DPM 0xa
105 #define I2C_DPM_ADDR 0x28
118 #define CONFIG_ENV_SPI_BUS 0
119 #define CONFIG_ENV_SPI_CS 0
121 #define CONFIG_ENV_SPI_MODE 0
122 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
123 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
124 #define CONFIG_ENV_SECT_SIZE 0x10000
127 #define CONFIG_SYS_MMC_ENV_DEV 0
128 #define CONFIG_ENV_SIZE 0x2000
132 #define CONFIG_ENV_SIZE 0x2000
135 #define CONFIG_ENV_ADDR 0xffe20000
136 #define CONFIG_ENV_SIZE 0x2000
138 #define CONFIG_ENV_SIZE 0x2000
141 #define CONFIG_ENV_SIZE 0x2000
142 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
160 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
170 #if 0
173 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
174 #define CONFIG_SYS_MEMTEST_END 0x00400000
180 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
192 #define CONFIG_SYS_DCSRBAR 0xf0000000
193 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
199 #define CONFIG_SYS_EEPROM_BUS_NUM 0
200 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
209 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
221 #define CONFIG_SYS_SPD_BUS_NUM 0
222 #define SPD_EEPROM_ADDRESS1 0x51
223 #define SPD_EEPROM_ADDRESS2 0x53
231 #define CONFIG_SYS_FLASH_BASE 0xe0000000
233 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
238 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
240 + 0x8000000) | \
244 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
252 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
253 FTIM0_NOR_TEADC(0x04) | \
254 FTIM0_NOR_TEAHC(0x20))
255 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
256 FTIM1_NOR_TRAD_NOR(0x1A) |\
257 FTIM1_NOR_TSEQRAD_NOR(0x13))
258 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \
259 FTIM2_NOR_TCH(0x0E) | \
260 FTIM2_NOR_TWPH(0x0E) | \
261 FTIM2_NOR_TWP(0x1c))
262 #define CONFIG_SYS_NOR_FTIM3 0x0
274 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
278 #define QIXIS_BASE 0xffdf0000
280 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
284 #define QIXIS_LBMAP_SWITCH 0x01
285 #define QIXIS_LBMAP_MASK 0x0f
286 #define QIXIS_LBMAP_SHIFT 0
287 #define QIXIS_LBMAP_DFLTBANK 0x00
288 #define QIXIS_LBMAP_ALTBANK 0x02
289 #define QIXIS_RST_CTL_RESET 0x31
290 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
291 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
292 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
294 #define CONFIG_SYS_CSPR3_EXT (0xf)
300 #define CONFIG_SYS_CSOR3 0x0
302 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
303 FTIM0_GPCM_TEADC(0x0e) | \
304 FTIM0_GPCM_TEAHC(0x0e))
305 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
306 FTIM1_GPCM_TRAD(0x1f))
307 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
308 FTIM2_GPCM_TCH(0x8) | \
309 FTIM2_GPCM_TWP(0x1f))
310 #define CONFIG_SYS_CS3_FTIM3 0x0
316 #define CONFIG_SYS_NAND_BASE 0xff800000
318 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
323 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
341 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
342 FTIM0_NAND_TWP(0x18) | \
343 FTIM0_NAND_TWCHT(0x07) | \
344 FTIM0_NAND_TWH(0x0a))
345 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
346 FTIM1_NAND_TWBE(0x39) | \
347 FTIM1_NAND_TRR(0x0e) | \
348 FTIM1_NAND_TRP(0x18))
349 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
350 FTIM2_NAND_TREH(0x0a) | \
351 FTIM2_NAND_TWHRE(0x1e))
352 #define CONFIG_SYS_NAND_FTIM3 0x0
423 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
425 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
426 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
432 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
433 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
436 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
452 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
457 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
458 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
459 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
460 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
466 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
468 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
469 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
470 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
477 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
484 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
486 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
488 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
490 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
494 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
496 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
498 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
500 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
508 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
509 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
510 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
511 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
516 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
517 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
518 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
521 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
522 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
528 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
530 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
537 #define CONFIG_SF_DEFAULT_MODE 0
543 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull
545 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000
550 * Memory space is mapped 1-1, but I/O space must start from 0.
554 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
556 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
557 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
559 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
560 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
562 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
563 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
564 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
566 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
568 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
570 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
576 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
578 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
582 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
583 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
584 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
590 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
592 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
594 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
598 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
599 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
600 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
606 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
615 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
616 * env, so we got 0x110000.
619 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
622 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
624 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
640 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
643 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
645 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
646 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
654 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
655 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
656 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
657 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
667 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
668 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
671 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/
672 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/
674 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
675 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
676 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
677 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
709 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
745 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
746 "netdev=eth0\0" \
747 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
748 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
754 "cmp.b $loadaddr $ubootaddr $filesize\0" \
755 "consoledev=ttyS0\0" \
756 "ramdiskaddr=2000000\0" \
757 "ramdiskfile=b4860qds/ramdisk.uboot\0" \
758 "fdtaddr=1e00000\0" \
759 "fdtfile=b4860qds/b4860qds.dtb\0" \
760 "bdev=sda3\0"
767 "cpu 1 release 0x29000000 - - -;" \
768 "cpu 2 release 0x29000000 - - -;" \
769 "cpu 3 release 0x29000000 - - -;" \
770 "cpu 4 release 0x29000000 - - -;" \
771 "cpu 5 release 0x29000000 - - -;" \
772 "cpu 6 release 0x29000000 - - -;" \
773 "cpu 7 release 0x29000000 - - -;" \
774 "go 0x29000000"
777 "setenv bootargs config-addr=0x60000000; " \
778 "bootm 0x01000000 - 0x00f00000"
783 "cpu 1 release 0x01000000 - - -;" \
784 "cpu 2 release 0x01000000 - - -;" \
785 "cpu 3 release 0x01000000 - - -;" \
786 "cpu 4 release 0x01000000 - - -;" \
787 "cpu 5 release 0x01000000 - - -;" \
788 "cpu 6 release 0x01000000 - - -;" \
789 "cpu 7 release 0x01000000 - - -;" \
790 "go 0x01000000"
795 "setenv ramdiskaddr 0x02000000;" \
796 "setenv fdtaddr 0x01e00000;" \
797 "setenv loadaddr 0x1000000;" \