Lines Matching +full:- +full:x
5 * SPDX-License-Identifier: GPL-2.0+
25 unsigned int rev; /* 0x00 - PCU Revision */
26 unsigned int spinfo; /* 0x04 - Scratch Pad Info */
27 unsigned int rsvd1[2]; /* 0x08-0x0C: Reserved */
28 unsigned int soc_id; /* 0x10 - SoC ID */
29 unsigned int soc_ahb; /* 0x14 - SoC AHB configuration */
30 unsigned int soc_apb; /* 0x18 - SoC APB configuration */
32 unsigned int dcsrcr0; /* 0x20 - Driving Capability
34 unsigned int dcsrcr1; /* 0x24 - Driving Capability
36 unsigned int dcsrcr2; /* 0x28 - Driving Capability
39 unsigned int mfpsr0; /* 0x30 - Multi-Func Port Setting 0 */
40 unsigned int mfpsr1; /* 0x34 - Multi-Func Port Setting 1 */
41 unsigned int dmaes; /* 0x38 - DMA Engine Selection */
43 unsigned int oscc; /* 0x40 - OSC Control */
44 unsigned int pwmcd; /* 0x44 - PWM Clock divider */
45 unsigned int socmisc; /* 0x48 - SoC Misc. */
46 unsigned int rsvd5[13]; /* 0x4C-0x7C: Reserved */
47 unsigned int bsmcr; /* 0x80 - BSM Controrl */
48 unsigned int bsmst; /* 0x84 - BSM Status */
49 unsigned int wes; /* 0x88 - Wakeup Event Sensitivity*/
50 unsigned int west; /* 0x8C - Wakeup Event Status */
51 unsigned int rsttiming; /* 0x90 - Reset Timing */
52 unsigned int intr_st; /* 0x94 - PCU Interrupt Status */
53 unsigned int rsvd6[2]; /* 0x98-0x9C: Reserved */
54 struct pcs pcs1; /* 0xA0-0xB0: PCS1 (clock scaling) */
55 unsigned int pcsrsvd1[3]; /* 0xB4-0xBC: Reserved */
56 struct pcs pcs2; /* 0xC0-0xD0: PCS2 (AHB clock gating) */
57 unsigned int pcsrsvd2[3]; /* 0xD4-0xDC: Reserved */
58 struct pcs pcs3; /* 0xE0-0xF0: PCS3 (APB clock gating) */
59 unsigned int pcsrsvd3[3]; /* 0xF4-0xFC: Reserved */
60 struct pcs pcs4; /* 0x100-0x110: PCS4 main PLL scaling */
61 unsigned int pcsrsvd4[3]; /* 0x114-0x11C: Reserved */
62 struct pcs pcs5; /* 0x120-0x130: PCS5 PCI PLL scaling */
63 unsigned int pcsrsvd5[3]; /* 0x134-0x13C: Reserved */
64 struct pcs pcs6; /* 0x140-0x150: PCS6 AC97 PLL scaling */
65 unsigned int pcsrsvd6[3]; /* 0x154-0x15C: Reserved */
66 struct pcs pcs7; /* 0x160-0x170: PCS7 GMAC PLL scaling */
67 unsigned int pcsrsvd7[3]; /* 0x174-0x17C: Reserved */
68 struct pcs pcs8; /* 0x180-0x190: PCS8 voltage scaling */
69 unsigned int pcsrsvd8[3]; /* 0x194-0x19C: Reserved */
70 struct pcs pcs9; /* 0x1A0-0x1B0: PCS9 power control */
71 unsigned int pcsrsvd9[93]; /* 0x1B4-0x3FC: Reserved */
72 unsigned int pmspdm[40]; /* 0x400-0x4fC: Power Manager
80 #define ANDES_PCU_REV_NUMBER_PCS(x) (((x) >> 0) & 0xff) argument
81 #define ANDES_PCU_REV_VER(x) (((x) >> 16) & 0xffff) argument
86 #define ANDES_PCU_SPINFO_SIZE(x) (((x) >> 0) & 0xff) argument
87 #define ANDES_PCU_SPINFO_OFFSET(x) (((x) >> 8) & 0xf) argument
92 #define ANDES_PCU_SOC_ID_VER_MINOR(x) (((x) >> 0) & 0xf) argument
93 #define ANDES_PCU_SOC_ID_VER_MAJOR(x) (((x) >> 4) & 0xfff) argument
94 #define ANDES_PCU_SOC_ID_DEVICEID(x) (((x) >> 16) & 0xffff) argument
99 #define ANDES_PCU_SOC_AHB_AHBC(x) ((x) << 0) argument
100 #define ANDES_PCU_SOC_AHB_APBREG(x) ((x) << 1) argument
101 #define ANDES_PCU_SOC_AHB_APB(x) ((x) << 2) argument
102 #define ANDES_PCU_SOC_AHB_DLM1(x) ((x) << 3) argument
103 #define ANDES_PCU_SOC_AHB_SPIROM(x) ((x) << 4) argument
104 #define ANDES_PCU_SOC_AHB_DDR2C(x) ((x) << 5) argument
105 #define ANDES_PCU_SOC_AHB_DDR2MEM(x) ((x) << 6) argument
106 #define ANDES_PCU_SOC_AHB_DMAC(x) ((x) << 7) argument
107 #define ANDES_PCU_SOC_AHB_DLM2(x) ((x) << 8) argument
108 #define ANDES_PCU_SOC_AHB_GPU(x) ((x) << 9) argument
109 #define ANDES_PCU_SOC_AHB_GMAC(x) ((x) << 12) argument
110 #define ANDES_PCU_SOC_AHB_IDE(x) ((x) << 13) argument
111 #define ANDES_PCU_SOC_AHB_USBOTG(x) ((x) << 14) argument
112 #define ANDES_PCU_SOC_AHB_INTC(x) ((x) << 15) argument
113 #define ANDES_PCU_SOC_AHB_LPCIO(x) ((x) << 16) argument
114 #define ANDES_PCU_SOC_AHB_LPCREG(x) ((x) << 17) argument
115 #define ANDES_PCU_SOC_AHB_PCIIO(x) ((x) << 18) argument
116 #define ANDES_PCU_SOC_AHB_PCIMEM(x) ((x) << 19) argument
117 #define ANDES_PCU_SOC_AHB_L2CC(x) ((x) << 20) argument
118 #define ANDES_PCU_SOC_AHB_AHB2AHBREG(x) ((x) << 27) argument
119 #define ANDES_PCU_SOC_AHB_AHB2AHBMEM0(x) ((x) << 28) argument
120 #define ANDES_PCU_SOC_AHB_AHB2AHBMEM1(x) ((x) << 29) argument
121 #define ANDES_PCU_SOC_AHB_AHB2AHBMEM2(x) ((x) << 30) argument
122 #define ANDES_PCU_SOC_AHB_AHB2AHBMEM3(x) ((x) << 31) argument
127 #define ANDES_PCU_SOC_APB_CFC(x) ((x) << 1) argument
128 #define ANDES_PCU_SOC_APB_SSP(x) ((x) << 2) argument
129 #define ANDES_PCU_SOC_APB_UART1(x) ((x) << 3) argument
130 #define ANDES_PCU_SOC_APB_SDC(x) ((x) << 5) argument
131 #define ANDES_PCU_SOC_APB_AC97I2S(x) ((x) << 6) argument
132 #define ANDES_PCU_SOC_APB_UART2(x) ((x) << 8) argument
133 #define ANDES_PCU_SOC_APB_PCU(x) ((x) << 16) argument
134 #define ANDES_PCU_SOC_APB_TMR(x) ((x) << 17) argument
135 #define ANDES_PCU_SOC_APB_WDT(x) ((x) << 18) argument
136 #define ANDES_PCU_SOC_APB_RTC(x) ((x) << 19) argument
137 #define ANDES_PCU_SOC_APB_GPIO(x) ((x) << 20) argument
138 #define ANDES_PCU_SOC_APB_I2C(x) ((x) << 22) argument
139 #define ANDES_PCU_SOC_APB_PWM(x) ((x) << 23) argument
144 #define ANDES_PCU_DCSRCR0_TRIAHB(x) (((x) & 0x1f) << 0) argument
145 #define ANDES_PCU_DCSRCR0_LPC(x) (((x) & 0xf) << 8) argument
146 #define ANDES_PCU_DCSRCR0_ULPI(x) (((x) & 0xf) << 12) argument
147 #define ANDES_PCU_DCSRCR0_GMAC(x) (((x) & 0xf) << 16) argument
148 #define ANDES_PCU_DCSRCR0_GPU(x) (((x) & 0xf) << 20) argument
153 #define ANDES_PCU_DCSRCR1_I2C(x) (((x) & 0xf) << 0) argument
158 #define ANDES_PCU_DCSRCR2_UART1(x) (((x) & 0xf) << 0) argument
159 #define ANDES_PCU_DCSRCR2_UART2(x) (((x) & 0xf) << 4) argument
160 #define ANDES_PCU_DCSRCR2_AC97(x) (((x) & 0xf) << 8) argument
161 #define ANDES_PCU_DCSRCR2_SPI(x) (((x) & 0xf) << 12) argument
162 #define ANDES_PCU_DCSRCR2_SD(x) (((x) & 0xf) << 16) argument
163 #define ANDES_PCU_DCSRCR2_CFC(x) (((x) & 0xf) << 20) argument
164 #define ANDES_PCU_DCSRCR2_GPIO(x) (((x) & 0xf) << 24) argument
165 #define ANDES_PCU_DCSRCR2_PCU(x) (((x) & 0xf) << 28) argument
168 * Multi-function Port Setting Register 0 (rw)
170 #define ANDES_PCU_MFPSR0_PCIMODE(x) ((x) << 0) argument
171 #define ANDES_PCU_MFPSR0_IDEMODE(x) ((x) << 1) argument
172 #define ANDES_PCU_MFPSR0_MINI_TC01(x) ((x) << 2) argument
173 #define ANDES_PCU_MFPSR0_AHB_DEBUG(x) ((x) << 3) argument
174 #define ANDES_PCU_MFPSR0_AHB_TARGET(x) ((x) << 4) argument
175 #define ANDES_PCU_MFPSR0_DEFAULT_IVB(x) (((x) & 0x7) << 28) argument
176 #define ANDES_PCU_MFPSR0_DEFAULT_ENDIAN(x) ((x) << 31) argument
179 * Multi-function Port Setting Register 1 (rw)
181 #define ANDES_PCU_MFPSR1_SUSPEND(x) ((x) << 0) argument
182 #define ANDES_PCU_MFPSR1_PWM0(x) ((x) << 1) argument
183 #define ANDES_PCU_MFPSR1_PWM1(x) ((x) << 2) argument
184 #define ANDES_PCU_MFPSR1_AC97CLKOUT(x) ((x) << 3) argument
185 #define ANDES_PCU_MFPSR1_PWREN(x) ((x) << 4) argument
186 #define ANDES_PCU_MFPSR1_PME(x) ((x) << 5) argument
187 #define ANDES_PCU_MFPSR1_I2C(x) ((x) << 6) argument
188 #define ANDES_PCU_MFPSR1_UART1(x) ((x) << 7) argument
189 #define ANDES_PCU_MFPSR1_UART2(x) ((x) << 8) argument
190 #define ANDES_PCU_MFPSR1_SPI(x) ((x) << 9) argument
191 #define ANDES_PCU_MFPSR1_SD(x) ((x) << 10) argument
192 #define ANDES_PCU_MFPSR1_GPUPLLSRC(x) ((x) << 27) argument
193 #define ANDES_PCU_MFPSR1_DVOMODE(x) ((x) << 28) argument
194 #define ANDES_PCU_MFPSR1_HSMP_FAST_REQ(x) ((x) << 29) argument
195 #define ANDES_PCU_MFPSR1_AHB_FAST_REQ(x) ((x) << 30) argument
196 #define ANDES_PCU_MFPSR1_PMUR_EXT_INT(x) ((x) << 31) argument
201 #define ANDES_PCU_DMAES_AC97RX(x) ((x) << 2) argument
202 #define ANDES_PCU_DMAES_AC97TX(x) ((x) << 3) argument
203 #define ANDES_PCU_DMAES_UART1RX(x) ((x) << 4) argument
204 #define ANDES_PCU_DMAES_UART1TX(x) ((x) << 5) argument
205 #define ANDES_PCU_DMAES_UART2RX(x) ((x) << 6) argument
206 #define ANDES_PCU_DMAES_UART2TX(x) ((x) << 7) argument
207 #define ANDES_PCU_DMAES_SDDMA(x) ((x) << 8) argument
208 #define ANDES_PCU_DMAES_CFCDMA(x) ((x) << 9) argument
213 #define ANDES_PCU_OSCC_OSCH_OFF(x) ((x) << 0) argument
214 #define ANDES_PCU_OSCC_OSCH_STABLE(x) ((x) << 1) argument
215 #define ANDES_PCU_OSCC_OSCH_TRI(x) ((x) << 2) argument
216 #define ANDES_PCU_OSCC_OSCH_RANGE(x) (((x) & 0x3) << 4) argument
217 #define ANDES_PCU_OSCC_OSCH2_RANGE(x) (((x) & 0x3) << 6) argument
218 #define ANDES_PCU_OSCC_OSCH3_RANGE(x) (((x) & 0x3) << 8) argument
223 #define ANDES_PCU_PWMCD_PWMDIV(x) (((x) & 0xf) << 0) argument
228 #define ANDES_PCU_SOCMISC_RSCPUA(x) ((x) << 0) argument
229 #define ANDES_PCU_SOCMISC_RSCPUB(x) ((x) << 1) argument
230 #define ANDES_PCU_SOCMISC_RSPCI(x) ((x) << 2) argument
231 #define ANDES_PCU_SOCMISC_USBWAKE(x) ((x) << 3) argument
232 #define ANDES_PCU_SOCMISC_EXLM_WAITA(x) (((x) & 0x3) << 4) argument
233 #define ANDES_PCU_SOCMISC_EXLM_WAITB(x) (((x) & 0x3) << 6) argument
234 #define ANDES_PCU_SOCMISC_DDRPLL_BYPASS(x) (((x) << 8) argument
235 #define ANDES_PCU_SOCMISC_300MHZSEL(x) (((x) << 9) argument
236 #define ANDES_PCU_SOCMISC_DDRDLL_SRST(x) (((x) << 10) argument
237 #define ANDES_PCU_SOCMISC_DDRDDQ_TEST(x) (((x) << 11) argument
238 #define ANDES_PCU_SOCMISC_DDRDLL_TEST(x) (((x) << 12) argument
239 #define ANDES_PCU_SOCMISC_GPUPLL_BYPASS(x) (((x) << 13) argument
240 #define ANDES_PCU_SOCMISC_ENCPUA(x) (((x) << 14) argument
241 #define ANDES_PCU_SOCMISC_ENCPUB(x) (((x) << 15) argument
242 #define ANDES_PCU_SOCMISC_PWON_PWBTN(x) (((x) << 16) argument
243 #define ANDES_PCU_SOCMISC_PWON_GPIO1(x) (((x) << 17) argument
244 #define ANDES_PCU_SOCMISC_PWON_GPIO2(x) (((x) << 18) argument
245 #define ANDES_PCU_SOCMISC_PWON_GPIO3(x) (((x) << 19) argument
246 #define ANDES_PCU_SOCMISC_PWON_GPIO4(x) (((x) << 20) argument
247 #define ANDES_PCU_SOCMISC_PWON_GPIO5(x) (((x) << 21) argument
248 #define ANDES_PCU_SOCMISC_PWON_WOL(x) (((x) << 22) argument
249 #define ANDES_PCU_SOCMISC_PWON_RTC(x) (((x) << 23) argument
250 #define ANDES_PCU_SOCMISC_PWON_RTCALM(x) (((x) << 24) argument
251 #define ANDES_PCU_SOCMISC_PWON_XDBGIN(x) (((x) << 25) argument
252 #define ANDES_PCU_SOCMISC_PWON_PME(x) (((x) << 26) argument
253 #define ANDES_PCU_SOCMISC_PWON_PWFAIL(x) (((x) << 27) argument
254 #define ANDES_PCU_SOCMISC_CPUA_SRSTED(x) (((x) << 28) argument
255 #define ANDES_PCU_SOCMISC_CPUB_SRSTED(x) (((x) << 29) argument
256 #define ANDES_PCU_SOCMISC_WD_RESET(x) (((x) << 30) argument
257 #define ANDES_PCU_SOCMISC_HW_RESET(x) (((x) << 31) argument
262 #define ANDES_PCU_BSMCR_LINK0(x) (((x) & 0xf) << 0) argument
263 #define ANDES_PCU_BSMCR_LINK1(x) (((x) & 0xf) << 4) argument
264 #define ANDES_PCU_BSMCR_SYNCSRC(x) (((x) & 0xf) << 24) argument
265 #define ANDES_PCU_BSMCR_CMD(x) (((x) & 0x7) << 28) argument
266 #define ANDES_PCU_BSMCR_IE(x) ((x) << 31) argument
271 #define ANDES_PCU_BSMSR_CI0(x) (((x) & 0xf) << 0) argument
272 #define ANDES_PCU_BSMSR_CI1(x) (((x) & 0xf) << 4) argument
273 #define ANDES_PCU_BSMSR_SYNCSRC(x) (((x) & 0xf) << 24) argument
274 #define ANDES_PCU_BSMSR_BSMST(x) (((x) & 0xf) << 28) argument
279 #define ANDES_PCU_WESR_POLOR(x) (((x) & 0xff) << 0) argument
284 #define ANDES_PCU_WEST_SIG(x) (((x) & 0xff) << 0) argument
289 #define ANDES_PCU_RSTTIMING_RG0(x) (((x) & 0xff) << 0) argument
290 #define ANDES_PCU_RSTTIMING_RG1(x) (((x) & 0xff) << 8) argument
291 #define ANDES_PCU_RSTTIMING_RG2(x) (((x) & 0xff) << 16) argument
292 #define ANDES_PCU_RSTTIMING_RG3(x) (((x) & 0xff) << 24) argument
297 #define ANDES_PCU_INTR_ST_BSM(x) ((x) << 0) argument
298 #define ANDES_PCU_INTR_ST_PCS1(x) ((x) << 1) argument
299 #define ANDES_PCU_INTR_ST_PCS2(x) ((x) << 2) argument
300 #define ANDES_PCU_INTR_ST_PCS3(x) ((x) << 3) argument
301 #define ANDES_PCU_INTR_ST_PCS4(x) ((x) << 4) argument
302 #define ANDES_PCU_INTR_ST_PCS5(x) ((x) << 5) argument
303 #define ANDES_PCU_INTR_ST_PCS6(x) ((x) << 6) argument
304 #define ANDES_PCU_INTR_ST_PCS7(x) ((x) << 7) argument
305 #define ANDES_PCU_INTR_ST_PCS8(x) ((x) << 8) argument
306 #define ANDES_PCU_INTR_ST_PCS9(x) ((x) << 9) argument
311 #define ANDES_PCU_PCSX_CR_WAKEUP_EN(x) (((x) & 0xff) << 0) argument
312 #define ANDES_PCU_PCSX_CR_LW(x) (((x) & 0xf) << 16) argument
313 #define ANDES_PCU_PCSX_CR_LS(x) (((x) & 0xf) << 20) argument
314 #define ANDES_PCU_PCSX_CR_TYPE(x) (((x) >> 28) & 0x7) /* (ro) */ argument
319 #define ANDES_PCU_PCSX_PARM_NEXT(x) (((x) & 0xffffff) << 0) argument
320 #define ANDES_PCU_PCSX_PARM_SYNCSRC(x) (((x) & 0xf) << 24) argument
321 #define ANDES_PCU_PCSX_PARM_PCSCMD(x) (((x) & 0x7) << 28) argument
322 #define ANDES_PCU_PCSX_PARM_IE(x) (((x) << 31) argument
327 #define ANDES_PCU_PCSX_STAT1_ERRNO(x) (((x) & 0xf) << 0) argument
328 #define ANDES_PCU_PCSX_STAT1_ST(x) (((x) & 0x7) << 28) argument
333 #define ANDES_PCU_PCSX_STAT2_CRNTPARM(x) (((x) & 0xffffff) << 0) argument
334 #define ANDES_PCU_PCSX_STAT2_SYNCSRC(x) (((x) & 0xf) << 24) argument
338 * This is reserved for PCS(1-7)
340 #define ANDES_PCU_PCS8_PDD_1BYTE(x) (((x) & 0xff) << 0) argument
341 #define ANDES_PCU_PCS8_PDD_2BYTE(x) (((x) & 0xff) << 8) argument
342 #define ANDES_PCU_PCS8_PDD_3BYTE(x) (((x) & 0xff) << 16) argument
343 #define ANDES_PCU_PCS8_PDD_4BYTE(x) (((x) & 0xff) << 24) argument
345 #define ANDES_PCU_PCS9_PDD_TIME1(x) (((x) & 0x3f) << 0) argument
346 #define ANDES_PCU_PCS9_PDD_TIME2(x) (((x) & 0x3f) << 6) argument
347 #define ANDES_PCU_PCS9_PDD_TIME3(x) (((x) & 0x3f) << 12) argument
348 #define ANDES_PCU_PCS9_PDD_TIME4(x) (((x) & 0x3f) << 18) argument
349 #define ANDES_PCU_PCS9_PDD_TICKTYPE(x) ((x) << 24) argument
350 #define ANDES_PCU_PCS9_PDD_GPU_SRST(x) ((x) << 27) argument
351 #define ANDES_PCU_PCS9_PDD_PWOFFTIME(x) (((x) & 0x3) << 28) argument
352 #define ANDES_PCU_PCS9_PDD_SUS2DRAM(x) ((x) << 30) argument
353 #define ANDES_PCU_PCS9_PDD_CLRPWOFF_FLAG(x) ((x) << 31) argument