Lines Matching +full:multi +full:- +full:word
2 * FILE SA-1100.h
8 * System StrongARM SA-1100
11 * SA-1100 microprocessor (Advanced RISC Machine (ARM)
13 * StrongARM SA-1100 data sheet version 2.2.
15 * Language-specific definitions are selected by the
33 #include <asm/arch-sa1100/bitfield.h>
42 typedef Word32 Word ; typedef
43 typedef Word Quad [4] ;
195 * Controller (UDC) Control/Status register end-point 0
198 * Controller (UDC) Control/Status register end-point 1
201 * Controller (UDC) Control/Status register end-point 2
204 * Controller (UDC) Data register end-point 0
207 * Controller (UDC) Write Count register end-point 0
222 /* reg. end-point 0 */
224 /* reg. end-point 1 (output) */
226 /* reg. end-point 2 (input) */
228 /* end-point 0 */
230 /* reg. end-point 0 */
236 (*((volatile Word *) io_p2v (_Ser0UDCCR)))
238 (*((volatile Word *) io_p2v (_Ser0UDCAR)))
241 (*((volatile Word *) io_p2v (_Ser0UDCOMP)))
244 (*((volatile Word *) io_p2v (_Ser0UDCIMP)))
246 /* reg. end-point 0 */ \
247 (*((volatile Word *) io_p2v (_Ser0UDCCS0)))
249 /* reg. end-point 1 (output) */ \
250 (*((volatile Word *) io_p2v (_Ser0UDCCS1)))
252 /* reg. end-point 2 (input) */ \
253 (*((volatile Word *) io_p2v (_Ser0UDCCS2)))
255 /* end-point 0 */ \
256 (*((volatile Word *) io_p2v (_Ser0UDCD0)))
258 /* reg. end-point 0 */ \
259 (*((volatile Word *) io_p2v (_Ser0UDCWC)))
261 (*((volatile Word *) io_p2v (_Ser0UDCDR)))
263 (*((volatile Word *) io_p2v (_Ser0UDCSR)))
269 #define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */
282 #define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */
286 (((Size) - 1) << FShft (UDCOMP_OUTMAXP))
288 #define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */
292 (((Size) - 1) << FShft (UDCIMP_INMAXP))
304 #define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */
312 #define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */
316 #define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */
326 #define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */
411 (0x80010000 + ((Nb) - 1)*0x00020000)
413 (0x80010004 + ((Nb) - 1)*0x00020000)
415 (0x80010008 + ((Nb) - 1)*0x00020000)
417 (0x8001000C + ((Nb) - 1)*0x00020000)
419 (0x80010010 + ((Nb) - 1)*0x00020000)
421 (0x80010014 + ((Nb) - 1)*0x00020000)
423 (0x8001001C + ((Nb) - 1)*0x00020000)
425 (0x80010020 + ((Nb) - 1)*0x00020000)
455 (*((volatile Word *) io_p2v (_Ser1UTCR0)))
457 (*((volatile Word *) io_p2v (_Ser1UTCR1)))
459 (*((volatile Word *) io_p2v (_Ser1UTCR2)))
461 (*((volatile Word *) io_p2v (_Ser1UTCR3)))
463 (*((volatile Word *) io_p2v (_Ser1UTDR)))
465 (*((volatile Word *) io_p2v (_Ser1UTSR0)))
467 (*((volatile Word *) io_p2v (_Ser1UTSR1)))
470 (*((volatile Word *) io_p2v (_Ser2UTCR0)))
472 (*((volatile Word *) io_p2v (_Ser2UTCR1)))
474 (*((volatile Word *) io_p2v (_Ser2UTCR2)))
476 (*((volatile Word *) io_p2v (_Ser2UTCR3)))
478 (*((volatile Word *) io_p2v (_Ser2UTCR4)))
480 (*((volatile Word *) io_p2v (_Ser2UTDR)))
482 (*((volatile Word *) io_p2v (_Ser2UTSR0)))
484 (*((volatile Word *) io_p2v (_Ser2UTSR1)))
487 (*((volatile Word *) io_p2v (_Ser3UTCR0)))
489 (*((volatile Word *) io_p2v (_Ser3UTCR1)))
491 (*((volatile Word *) io_p2v (_Ser3UTCR2)))
493 (*((volatile Word *) io_p2v (_Ser3UTCR3)))
495 (*((volatile Word *) io_p2v (_Ser3UTDR)))
497 (*((volatile Word *) io_p2v (_Ser3UTSR0)))
499 (*((volatile Word *) io_p2v (_Ser3UTSR1)))
537 #define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */
538 #define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */
543 #define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */
544 #define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */
546 #define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */
547 #define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */
551 #define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
552 #define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
556 (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \
559 (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \
564 (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \
567 (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \
575 #define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
577 #define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
579 #define UTCR3_LBM 0x00000020 /* Look-Back Mode */
584 #define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */
585 /* (HP-SIR) modulation Enable */
586 #define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */
587 #define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */
588 #define UTCR4_LPM 0x00000002 /* Low-Power Mode */
596 #define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
599 #define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */
601 #define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */
613 #define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */
654 (*((volatile Word *) io_p2v (_Ser1SDCR0)))
656 (*((volatile Word *) io_p2v (_Ser1SDCR1)))
658 (*((volatile Word *) io_p2v (_Ser1SDCR2)))
660 (*((volatile Word *) io_p2v (_Ser1SDCR3)))
662 (*((volatile Word *) io_p2v (_Ser1SDCR4)))
664 (*((volatile Word *) io_p2v (_Ser1SDDR)))
666 (*((volatile Word *) io_p2v (_Ser1SDSR0)))
668 (*((volatile Word *) io_p2v (_Ser1SDSR1)))
677 #define SDCR0_LBM 0x00000004 /* Look-Back Mode */
680 #define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */
687 #define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */
688 #define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */
690 #define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */
691 #define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */
697 #define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
699 #define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
702 #define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */
703 #define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */
704 #define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */
709 #define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
710 #define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
714 (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \
717 (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \
722 (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \
725 (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \
732 #define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
734 #define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
738 #define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
740 #define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
742 #define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */
750 #define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */
752 #define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */
756 * High-Speed Serial to Parallel controller (HSSP) control registers
759 * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel
761 * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel
763 * Ser2HSDR Serial port 2 High-Speed Serial to Parallel
765 * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel
767 * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel
769 * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel
773 * SA-1100.]
785 (*((volatile Word *) io_p2v (_Ser2HSCR0)))
787 (*((volatile Word *) io_p2v (_Ser2HSCR1)))
789 (*((volatile Word *) io_p2v (_Ser2HSDR)))
791 (*((volatile Word *) io_p2v (_Ser2HSSR0)))
793 (*((volatile Word *) io_p2v (_Ser2HSSR1)))
795 (*((volatile Word *) io_p2v (_Ser2HSCR2)))
801 #define HSCR0_LBM 0x00000002 /* Look-Back Mode */
802 #define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */
803 #define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */
804 #define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */
807 #define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */
809 #define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */
817 #define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
819 #define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
823 #define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
825 #define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
827 #define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */
835 #define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */
837 #define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */
843 /* (non-inverted) */
848 /* (non-inverted) */
852 * Multi-media Communications Port (MCP) control registers
855 * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP)
857 * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP)
859 * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP)
861 * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP)
863 * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP)
865 * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP)
869 * SA-1100.]
890 (*((volatile Word *) io_p2v (_Ser4MCCR0)))
893 (*((volatile Word *) io_p2v (_Ser4MCDR0)))
896 (*((volatile Word *) io_p2v (_Ser4MCDR1)))
899 (*((volatile Word *) io_p2v (_Ser4MCDR2)))
901 (*((volatile Word *) io_p2v (_Ser4MCSR)))
903 (*((volatile Word *) io_p2v (_Ser4MCCR1)))
940 #define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */
942 #define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */
944 #define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */
946 #define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */
948 #define MCCR0_LBM 0x00800000 /* Look-Back Mode */
949 #define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */
951 (((Div) - 1) << FShft (MCCR0_ECP))
967 #define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */
969 #define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */
971 #define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */
973 #define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */
975 #define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */
976 #define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */
977 #define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */
978 #define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */
1010 * (rev. = 8) and higher of the StrongARM SA-1100.]
1029 (*((volatile Word *) io_p2v (_Ser4SSCR0)))
1031 (*((volatile Word *) io_p2v (_Ser4SSCR1)))
1033 (*((volatile Word *) io_p2v (_Ser4SSDR)))
1035 (*((volatile Word *) io_p2v (_Ser4SSSR)))
1038 #define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */
1040 (((Size) - 1) << FShft (SSCR0_DSS))
1051 #define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */
1055 (((Div) - 2)/2 << FShft (SSCR0_SCR))
1059 (((Div) - 1)/2 << FShft (SSCR0_SCR))
1063 #define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */
1065 #define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */
1067 #define SSCR1_LBM 0x00000004 /* Look-Back Mode */
1085 #define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */
1087 #define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */
1089 #define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */
1108 * OWER Operating System (OS) timer Watch-dog Enable Register
1122 #define _OWER 0x90000018 /* OS timer Watch-dog Enable Reg. */
1127 ((volatile Word *) io_p2v (_OSMR (0)))
1133 (*((volatile Word *) io_p2v (_OSCR)))
1135 (*((volatile Word *) io_p2v (_OSSR)))
1136 #define OWER /* OS timer Watch-dog Enable Reg. */ \
1137 (*((volatile Word *) io_p2v (_OWER)))
1139 (*((volatile Word *) io_p2v (_OIER)))
1149 #define OWER_WME 0x00000001 /* Watch-dog Match Enable */
1161 * Real-Time Clock (RTC) control registers
1164 * RTAR Real-Time Clock (RTC) Alarm Register (read/write).
1165 * RCNR Real-Time Clock (RTC) CouNt Register (read/write).
1166 * RTTR Real-Time Clock (RTC) Trim Register (read/write).
1167 * RTSR Real-Time Clock (RTC) Status Register (read/write).
1170 * frtx, Trtx Frequency, period of the real-time clock crystal
1172 * frtc, Trtc Frequency, period of the real-time clock counter
1183 (*((volatile Word *) io_p2v (_RTAR)))
1185 (*((volatile Word *) io_p2v (_RCNR)))
1187 (*((volatile Word *) io_p2v (_RTTR)))
1189 (*((volatile Word *) io_p2v (_RTSR)))
1192 #define RTTR_C Fld (16, 0) /* clock divider Count - 1 */
1194 /* frtc = (1023*(C + 1) - D)*frtx/ */
1197 /* (1023*(C + 1) - D) */
1211 * PSPR Power Manager (PM) Scratch-Pad Register (read/write).
1212 * PWER Power Manager (PM) Wake-up Enable Register
1216 * PPCR Power Manager (PM) Phase-Locked Loop (PLL)
1218 * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO)
1230 #define _PSPR 0x90020008 /* PM Scratch-Pad Reg. */
1231 #define _PWER 0x9002000C /* PM Wake-up Enable Reg. */
1239 (*((volatile Word *) io_p2v (_PMCR)))
1241 (*((volatile Word *) io_p2v (_PSSR)))
1242 #define PSPR /* PM Scratch-Pad Reg. */ \
1243 (*((volatile Word *) io_p2v (_PSPR)))
1244 #define PWER /* PM Wake-up Enable Reg. */ \
1245 (*((volatile Word *) io_p2v (_PWER)))
1247 (*((volatile Word *) io_p2v (_PCFR)))
1249 (*((volatile Word *) io_p2v (_PPCR)))
1251 (*((volatile Word *) io_p2v (_PGSR)))
1253 (*((volatile Word *) io_p2v (_POSR)))
1276 #define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */
1277 #define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
1278 #define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
1279 #define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
1280 #define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
1281 #define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
1282 #define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
1283 #define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
1284 #define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
1285 #define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
1286 #define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
1287 #define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
1288 #define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
1289 #define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
1290 #define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
1291 #define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
1292 #define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
1293 #define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */
1294 #define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */
1295 #define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */
1296 #define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */
1297 #define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */
1298 #define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */
1299 #define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */
1300 #define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */
1301 #define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */
1302 #define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */
1303 #define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */
1304 #define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */
1305 #define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
1307 #define PCFR_OPDE 0x00000001 /* Oscillator Power-Down Enable */
1404 (*((volatile Word *) io_p2v (_RSRR)))
1406 (*((volatile Word *) io_p2v (_RCSR)))
1413 #define RCSR_WDR 0x00000004 /* Watch-Dog Reset */
1414 #define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */
1428 (*((volatile Word *) io_p2v (_TUCR)))
1467 * General-Purpose Input/Output (GPIO) control registers
1470 * GPLR General-Purpose Input/Output (GPIO) Pin Level
1472 * GPDR General-Purpose Input/Output (GPIO) Pin Direction
1474 * GPSR General-Purpose Input/Output (GPIO) Pin output Set
1476 * GPCR General-Purpose Input/Output (GPIO) Pin output Clear
1478 * GRER General-Purpose Input/Output (GPIO) Rising-Edge
1480 * GFER General-Purpose Input/Output (GPIO) Falling-Edge
1482 * GEDR General-Purpose Input/Output (GPIO) Edge Detect
1484 * GAFR General-Purpose Input/Output (GPIO) Alternate
1495 #define _GRER 0x90040010 /* GPIO Rising-Edge detect Reg. */
1496 #define _GFER 0x90040014 /* GPIO Falling-Edge detect Reg. */
1502 (*((volatile Word *) io_p2v (_GPLR)))
1504 (*((volatile Word *) io_p2v (_GPDR)))
1506 (*((volatile Word *) io_p2v (_GPSR)))
1508 (*((volatile Word *) io_p2v (_GPCR)))
1509 #define GRER /* GPIO Rising-Edge detect Reg. */ \
1510 (*((volatile Word *) io_p2v (_GRER)))
1511 #define GFER /* GPIO Falling-Edge detect Reg. */ \
1512 (*((volatile Word *) io_p2v (_GFER)))
1514 (*((volatile Word *) io_p2v (_GEDR)))
1516 (*((volatile Word *) io_p2v (_GAFR)))
1565 GPIO_GPIO ((Nb) - 6)
1616 * (rev. = 8) and higher of the StrongARM SA-1100.]
1622 * StrongARM SA-1100, it is active high (non-inverted) in
1635 (*((volatile Word *) io_p2v (_ICIP)))
1637 (*((volatile Word *) io_p2v (_ICMR)))
1639 (*((volatile Word *) io_p2v (_ICLR)))
1641 (*((volatile Word *) io_p2v (_ICCR)))
1643 (*((volatile Word *) io_p2v (_ICFP)))
1645 (*((volatile Word *) io_p2v (_ICPR)))
1690 #define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */
1692 #define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */
1694 #define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */
1708 * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin
1717 #define _PSDR 0x9006000C /* PPC Sleep-mode pin Direction */
1723 (*((volatile Word *) io_p2v (_PPDR)))
1725 (*((volatile Word *) io_p2v (_PPSR)))
1727 (*((volatile Word *) io_p2v (_PPAR)))
1728 #define PSDR /* PPC Sleep-mode pin Direction */ \
1730 (*((volatile Word *) io_p2v (_PSDR)))
1732 (*((volatile Word *) io_p2v (_PPFR)))
1793 * Dynamic Random-Access Memory (DRAM) control registers
1796 * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM)
1798 * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM)
1801 * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM)
1804 * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM)
1825 (*((volatile Word *) io_p2v (_MDCNFG)))
1827 ((volatile Word *) io_p2v (_MDCAS (0)))
1845 #define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */
1847 (((Add) - 9) << FShft (MDCNFG_DRAC))
1850 #define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */
1851 #define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \
1852 (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP))
1854 (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP))
1855 #define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */
1857 (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR))
1859 (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR))
1920 ((volatile Word *) io_p2v (_MSC (0)))
1923 #define MSC2 (*(volatile Word *) io_p2v (_MSC2)) /* Static memory Control reg. 2 */
1941 #define MSC_NonBrst /* Non-Burst static memory */ \
1943 #define MSC_SRAM /* 32-bit byte-writable SRAM */ \
1945 #define MSC_Brst4 /* Burst-of-4 static memory */ \
1947 #define MSC_Brst8 /* Burst-of-8 static memory */ \
1950 #define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */
1951 #define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */
1953 /* First access - 1(.5) [Tmem] */
1956 ((((Tcpu) - 3)/2) << FShft (MSC_RDF))
1958 ((((Tcpu) - 2)/2) << FShft (MSC_RDF))
1959 #define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \
1961 ((((Tcpu) - 2)/2) << FShft (MSC_RDF))
1963 ((((Tcpu) - 1)/2) << FShft (MSC_RDF))
1965 /* Next access - 1 [Tmem] */
1968 ((((Tcpu) - 2)/2) << FShft (MSC_RDN))
1970 ((((Tcpu) - 1)/2) << FShft (MSC_RDN))
1971 #define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \
1973 ((((Tcpu) - 2)/2) << FShft (MSC_RDN))
1975 ((((Tcpu) - 1)/2) << FShft (MSC_RDN))
2006 (*((volatile Word *) io_p2v (_MECR)))
2014 #define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */
2016 ((((Tcpu) - 2)/2) << FShft (MECR_BSIO))
2018 ((((Tcpu) - 1)/2) << FShft (MECR_BSIO))
2019 #define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */
2022 ((((Tcpu) - 2)/2) << FShft (MECR_BSA))
2024 ((((Tcpu) - 1)/2) << FShft (MECR_BSA))
2025 #define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */
2027 ((((Tcpu) - 2)/2) << FShft (MECR_BSM))
2029 ((((Tcpu) - 1)/2) << FShft (MECR_BSM))
2040 (*((volatile Word *) io_p2v (_MDREFR)))
2279 (*((volatile Word *) io_p2v (_DDAR0)))
2282 (*((volatile Word *) io_p2v (_SetDCSR0)))
2285 (*((volatile Word *) io_p2v (_ClrDCSR0)))
2288 (*((volatile Word *) io_p2v (_RdDCSR0)))
2294 (*((volatile Word *) io_p2v (_DBTA0)))
2300 (*((volatile Word *) io_p2v (_DBTB0)))
2304 (*((volatile Word *) io_p2v (_DDAR1)))
2307 (*((volatile Word *) io_p2v (_SetDCSR1)))
2310 (*((volatile Word *) io_p2v (_ClrDCSR1)))
2313 (*((volatile Word *) io_p2v (_RdDCSR1)))
2319 (*((volatile Word *) io_p2v (_DBTA1)))
2325 (*((volatile Word *) io_p2v (_DBTB1)))
2329 (*((volatile Word *) io_p2v (_DDAR2)))
2332 (*((volatile Word *) io_p2v (_SetDCSR2)))
2335 (*((volatile Word *) io_p2v (_ClrDCSR2)))
2338 (*((volatile Word *) io_p2v (_RdDCSR2)))
2344 (*((volatile Word *) io_p2v (_DBTA2)))
2350 (*((volatile Word *) io_p2v (_DBTB2)))
2354 (*((volatile Word *) io_p2v (_DDAR3)))
2357 (*((volatile Word *) io_p2v (_SetDCSR3)))
2360 (*((volatile Word *) io_p2v (_ClrDCSR3)))
2363 (*((volatile Word *) io_p2v (_RdDCSR3)))
2369 (*((volatile Word *) io_p2v (_DBTA3)))
2375 (*((volatile Word *) io_p2v (_DBTB3)))
2379 (*((volatile Word *) io_p2v (_DDAR4)))
2382 (*((volatile Word *) io_p2v (_SetDCSR4)))
2385 (*((volatile Word *) io_p2v (_ClrDCSR4)))
2388 (*((volatile Word *) io_p2v (_RdDCSR4)))
2394 (*((volatile Word *) io_p2v (_DBTA4)))
2400 (*((volatile Word *) io_p2v (_DBTB4)))
2404 (*((volatile Word *) io_p2v (_DDAR5)))
2407 (*((volatile Word *) io_p2v (_SetDCSR5)))
2410 (*((volatile Word *) io_p2v (_ClrDCSR5)))
2413 (*((volatile Word *) io_p2v (_RdDCSR5)))
2419 (*((volatile Word *) io_p2v (_DBTA5)))
2425 (*((volatile Word *) io_p2v (_DBTB5)))
2431 /* (memory -> device) */
2433 /* (device -> memory) */
2438 #define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */
2439 #define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */
2441 #define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */
2442 #define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */
2483 (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2)))
2565 * SA-1100.]
2569 * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be
2584 * StrongARM SA-1100, it can be written and read in
2590 * StrongARM SA-1100, it can be written and read in
2596 * StrongARM SA-1100, it can be written and read in
2599 * the StrongARM SA-1100.]
2610 #define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \
2613 #define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \
2616 #define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \
2617 /* dummy-Palette Space [byte] */ \
2625 #define LCD_4Bit /* LCD 4-Bit pixel mode */ \
2627 #define LCD_8Bit /* LCD 8-Bit pixel mode */ \
2629 #define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \
2666 (*((volatile Word *) io_p2v (_LCCR0)))
2668 (*((volatile Word *) io_p2v (_LCSR)))
2682 (*((volatile Word *) io_p2v (_LCCR1)))
2684 (*((volatile Word *) io_p2v (_LCCR2)))
2686 (*((volatile Word *) io_p2v (_LCCR3)))
2712 #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */
2714 #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */
2726 #define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */
2728 #define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */
2730 #define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */
2732 #define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */
2734 #define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */
2736 #define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */
2738 #define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */
2740 #define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */
2743 #define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */
2745 (((Pixel) - 16)/16 << FShft (LCCR1_PPL))
2747 /* pulse Width - 2 [Tpix] (L_LCLK) */
2750 (((Tpix) - 2) << FShft (LCCR1_HSW))
2751 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
2752 /* count - 1 [Tpix] */
2753 #define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
2755 (((Tpix) - 1) << FShft (LCCR1_ELW))
2756 #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
2757 /* Wait count - 1 [Tpix] */
2758 #define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
2760 (((Tpix) - 1) << FShft (LCCR1_BLW))
2762 #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
2764 (((Line) - 1) << FShft (LCCR2_LPP))
2766 /* Width - 1 [Tln] (L_FCLK) */
2769 (((Tln) - 1) << FShft (LCCR2_VSW))
2770 #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
2772 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
2775 #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
2777 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
2781 #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */
2786 (((Div) - 4)/2 << FShft (LCCR3_PCD))
2790 (((Div) - 3)/2 << FShft (LCCR3_PCD))
2793 #define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */
2796 (((Div) - 2)/2 << FShft (LCCR3_ACB))
2800 (((Div) - 1)/2 << FShft (LCCR3_ACB))
2824 #define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
2825 #define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */