48 	debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0));  in rkspi_dump_regs()
140 	uint ctrlr0;  in rockchip_spi_claim_bus()  local
165 	ctrlr0 = OMOD_MASTER << OMOD_SHIFT;  in rockchip_spi_claim_bus()
168 	ctrlr0 |= spi_dfs << DFS_SHIFT;  in rockchip_spi_claim_bus()
172 		ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;  in rockchip_spi_claim_bus()
174 		ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;  in rockchip_spi_claim_bus()
177 	ctrlr0 |= CSM_KEEP << CSM_SHIFT;  in rockchip_spi_claim_bus()
180 	ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;  in rockchip_spi_claim_bus()
183 	ctrlr0 |= SEM_LITTLE << SEM_SHIFT;  in rockchip_spi_claim_bus()
186 	ctrlr0 |= FBM_MSB << FBM_SHIFT;  in rockchip_spi_claim_bus()
189 	ctrlr0 |= spi_tf << HALF_WORD_TX_SHIFT;  in rockchip_spi_claim_bus()
192 	ctrlr0 |= priv->rsd << RXDSD_SHIFT;  in rockchip_spi_claim_bus()
195 	ctrlr0 |= FRF_SPI << FRF_SHIFT;  in rockchip_spi_claim_bus()
198 	priv->cr0 = ctrlr0;  in rockchip_spi_claim_bus()
200 	writel(ctrlr0, &regs->ctrlr0);  in rockchip_spi_claim_bus()
208 	uint ctrlr0 = priv->cr0;  in rockchip_spi_config()  local
216 	ctrlr0 |= (tmod & TMOD_MASK) << TMOD_SHIFT;  in rockchip_spi_config()
217 	writel(ctrlr0, &regs->ctrlr0);  in rockchip_spi_config()